FPGAs tend to have lots of pins… So to make it a little simpler, let's put them into two bins: “user pins” and “dedicated pins”.

用户管脚 The user pins are called “IOs”, or “I/Os”, or “user I/Os”, or “user IOs”, or “IO pins”, or … you get the idea. IO stands for “input-output”.

• You usually have total control over user IOs. They can be programmed to be inputs, outputs, or bi-directional (i.e. with tri-statable buffers).
• Each IO pin is connected to an “IO cell” inside the FPGA. The “IO cells” are powered by the VCCIO pins (IO power pins) - more details below.

固定管脚 The “dedicated pins” are hard-coded to a specific function. They fall into the three following sub-categories.

• 电源管脚
• 配制管脚: used to “download” the FPGA.
• 固定输入或时钟管脚: these are able to drive large nets inside the FPGA, suitable for clocks or signals with large fan-outs.

The power pins fall into two categories: “core voltage” and “IO voltage”.

• The core voltage is named “VCC” for Xilinx and “VCCINT” for Altera. It is fixed (set by the model of FPGA that you are using). It is used to power the logic gates and flip-flops inside the FPGA. The voltage was 5V for older FPGA generations, and is coming down as new generations come (3.3V, 2.5V, 1.8V, 1.5V, 1.2V and even lower for the latest devices).
• The IO voltage is named “VCCO” for Xilinx and “VCCIO” for Altera. It is used to power the I/O blocks (= pins) of the FPGA. That voltage should match what the other devices connected to the FPGA expect.

An FPGA has many VCCIO pins that may be all powered by the same voltage. But new generations of FPGAs have a concept of “user IO banks”: the IOs are split into groups, each having its own VCCIO pins. That allows using the FPGA as a voltage translator device, useful for example if one part of your board works with 3.3V logic, and another with 2.5V.