#Build: Synplify Pro I-2013.09L , Build 064R, Nov 15 2013 #install: C:\lscc\iCEcube2.2013.12\synpbase #OS: Windows 7 6.1 #Hostname: L25401 #Implementation: sdr_sdram_controller_Implmnt $ Start of Compile #Thu Mar 06 12:10:51 2014 Synopsys Verilog Compiler, version comp201309rc, Build 136R, built Nov 18 2013 @N: : | Running in 64-bit mode Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. @I::"C:\lscc\iCEcube2.2013.12\synpbase\lib\generic\sb_ice40.v" @I::"C:\lscc\iCEcube2.2013.12\synpbase\lib\vlog\umr_capim.v" @I::"C:\lscc\iCEcube2.2013.12\synpbase\lib\vlog\scemi_objects.v" @I::"C:\lscc\iCEcube2.2013.12\synpbase\lib\vlog\scemi_pipes.svh" @I::"C:\lscc\iCEcube2.2013.12\synpbase\lib\vlog\hypermods.v" @I::"G:\VEERAJ\RD\WORKING\RD1174\source\Verilog\Micron8M16\autorefresh_counter.v" @I:"G:\VEERAJ\RD\WORKING\RD1174\source\Verilog\Micron8M16\autorefresh_counter.v":"G:\VEERAJ\RD\WORKING\RD1174\source\Verilog\Micron8M16\sdram_defines.v" @I::"G:\VEERAJ\RD\WORKING\RD1174\source\Verilog\Micron8M16\delay_gen150us.v" @I::"G:\VEERAJ\RD\WORKING\RD1174\source\Verilog\Micron8M16\lfsr_count255.v" @I::"G:\VEERAJ\RD\WORKING\RD1174\source\Verilog\Micron8M16\lfsr_count64.v" @I::"G:\VEERAJ\RD\WORKING\RD1174\source\Verilog\Micron8M16\sdram_control_fsm.v" @I::"G:\VEERAJ\RD\WORKING\RD1174\source\Verilog\Micron8M16\sdram_controller.v" Verilog syntax check successful! Selecting top level module sdram_controller @N:CG364 : sdram_control_fsm.v(46) | Synthesizing module sdram_control_fsm WRITE_BURST_PROGRAMED_LENGTH=1'b0 WRITE_BURST_SINGLE_ACCESS=1'b1 SDRAM_STANDARD_MODE=2'b00 SDRAM_BURST_SEQUENTIAL=1'b0 SDRAM_BURST_INTERLEAVE=1'b1 SDRAM_CMD_INHIBIT=5'b11111 SDRAM_CMD_NOP=5'b01110 SDRAM_CMD_ACTIVE=5'b00111 SDRAM_CMD_READ=5'b01010 SDRAM_CMD_WRITE=5'b01000 SDRAM_CMD_BURSTSTOP=5'b01100 SDRAM_CMD_PRECHARGE=5'b00101 SDRAM_CMD_AUTOREFRESH=5'b00011 SDRAM_CMD_LOAD_MODEREG=5'b00001 SDRAM_CMD_SELFREFRESH=5'b00011 CMD_STATE_IDLE=5'b00000 CMD_STATE_ACTIVE2RW_DELAY=5'b10000 CMD_STATE_CAS_LATENCY=5'b11000 CMD_STATE_READ_DATA=5'b11100 CMD_STATE_WRITE_DATA=5'b11110 CMD_STATE_AUTOREFRESH_DELAY=5'b11111 CMD_STATE_DATAIN2ACTIVE=5'b01111 CMD_STATE_ACTIVE=5'b01110 CMD_STATE_READ_AUTOPRECHARGE=5'b00110 CMD_STATE_WRITE_AUTOPRECHARGE=5'b00010 CMD_STATE_AUTOREFRESH=5'b00011 CMD_STATE_LOAD_MODEREG=5'b01011 CMD_STATE_LOAD_MODEREG_DELAY=5'b01001 CMD_STATE_SELFREFRESH=5'b00001 CMD_STATE_SELFREFRESH_DELAY=5'b00101 CMD_STATE_BURSTSTOP_WRITE=5'b00111 CMD_STATE_BURSTSTOP_WRITE_DELAY=5'b10111 CMD_STATE_BURSTSTOP_READ=5'b10101 CMD_STATE_BURSTSTOP_READ_DELAY=5'b10001 CMD_STATE_PRECHARGE=5'b11001 CMD_STATE_PRECHARGE_DELAY=5'b11101 CMD_STATE_POWER_DOWN_MODE=5'b01101 INIT_STATE_IDLE=4'b0000 INIT_STATE_PRECHARGEALL=4'b0001 INIT_STATE_PRECHARGE_DELAY=4'b0010 INIT_STATE_AUTOREFRESH_1=4'b0011 INIT_STATE_AUTOREFRESH_DELAY_1=4'b0100 INIT_STATE_AUTOREFRESH_2=4'b0101 INIT_STATE_AUTOREFRESH_DELAY_2=4'b0110 INIT_STATE_LOAD_MODEREG=4'b0111 INIT_STATE_LOAD_MODEREG_DELAY=4'b1000 INIT_STATE_INIT_DONE=4'b1001 CPU_DATA_WIDTH=32'b00000000000000000000000000010000 SDRAM_ROW_WIDTH=32'b00000000000000000000000000001100 SDRAM_COL_WIDTH=32'b00000000000000000000000000001001 BLKADDR_MSB=32'b00000000000000000000000000001010 BLKADDR_LSB=32'b00000000000000000000000000001001 COLADDR_MSB=32'b00000000000000000000000000001000 COLADDR_LSB=32'b00000000000000000000000000000000 READ_REQ_CNT_WIDTH=32'b00000000000000000000000000001010 WIREDLY=32'b00000000000000000000000000000001 SDRAM_DATA_WIDTH=32'b00000000000000000000000000010000 CPU_ADDR_WIDTH=32'b00000000000000000000000000010110 SDRAM_ADDR_WIDTH=32'b00000000000000000000000000001100 SDRAM_BLKADR_WIDTH=32'b00000000000000000000000000000010 SDRAM_DQM_WIDTH=32'b00000000000000000000000000000010 ROWADDR_MSB=32'b00000000000000000000000000010110 ROWADDR_LSB=32'b00000000000000000000000000001010 AUTO_REFRESH_COUNT=32'b00000000000000000000010111011100 NUM_CLK_WRITE=32'b00000000000000000000000000000100 NUM_CLK_READ=32'b00000000000000000000000000000100 NUM_CLK_PRECHARGE_PERIOD=32'b00000000000000000000000000000010 NUM_CLK_AUTOREFRESH_PERIOD=32'b00000000000000000000000000000111 NUM_CLK_LOAD_MODEREG_DELAY=32'b00000000000000000000000000000010 NUM_CLK_ACTIVE2RW_DELAY=32'b00000000000000000000000000000010 NUM_CLK_CL=32'b00000000000000000000000000000010 NUM_CLK_WAIT=32'b00000000000000000000000000000001 NUM_CLK_SELFREFRESH2ACTIVE=32'b00000000000000000000000000000101 NUM_CLK_WRITE_RECOVERY_DELAY=32'b00000000000000000000000000000010 MODEREG_BURST_LENGTH=3'b010 SDRAM_BURST_PAGE=3'b111 MODEREG_WRITE_BURST_MODE=1'b0 MODEREG_OPERATION_MODE=2'b00 MODEREG_CAS_LATENCY=32'b00000000000000000000000000000010 MODEREG_BURST_TYPE=1'b0 Generated name = sdram_control_fsm_Z1 @W:CG360 : sdram_control_fsm.v(617) | No assignment to wire sdram_dq_reg0_i @W:CG360 : sdram_control_fsm.v(618) | No assignment to wire sdram_dq_reg1_i @W:CG360 : sdram_control_fsm.v(619) | No assignment to wire sdram_dq_reg2_i @W:CG360 : sdram_control_fsm.v(620) | No assignment to wire sdram_dq_reg3_i @W:CL169 : sdram_control_fsm.v(691) | Pruning register cpu_data_reg_i[15:0] @W:CL169 : sdram_control_fsm.v(671) | Pruning register cpu2sdram_reg_i[15:0] @W:CL189 : sdram_control_fsm.v(781) | Register bit o_sdram_csn is always 0, optimizing ... @N:CG364 : lfsr_count64.v(42) | Synthesizing module lfsr_count64 @N:CG364 : lfsr_count255.v(43) | Synthesizing module lfsr_count255 @N:CG364 : delay_gen150us.v(44) | Synthesizing module delay_gen150us @N:CG364 : autorefresh_counter.v(44) | Synthesizing module autorefresh_counter WRITE_BURST_PROGRAMED_LENGTH=1'b0 WRITE_BURST_SINGLE_ACCESS=1'b1 SDRAM_STANDARD_MODE=2'b00 SDRAM_BURST_SEQUENTIAL=1'b0 SDRAM_BURST_INTERLEAVE=1'b1 SDRAM_CMD_INHIBIT=5'b11111 SDRAM_CMD_NOP=5'b01110 SDRAM_CMD_ACTIVE=5'b00111 SDRAM_CMD_READ=5'b01010 SDRAM_CMD_WRITE=5'b01000 SDRAM_CMD_BURSTSTOP=5'b01100 SDRAM_CMD_PRECHARGE=5'b00101 SDRAM_CMD_AUTOREFRESH=5'b00011 SDRAM_CMD_LOAD_MODEREG=5'b00001 SDRAM_CMD_SELFREFRESH=5'b00011 CMD_STATE_IDLE=5'b00000 CMD_STATE_ACTIVE2RW_DELAY=5'b10000 CMD_STATE_CAS_LATENCY=5'b11000 CMD_STATE_READ_DATA=5'b11100 CMD_STATE_WRITE_DATA=5'b11110 CMD_STATE_AUTOREFRESH_DELAY=5'b11111 CMD_STATE_DATAIN2ACTIVE=5'b01111 CMD_STATE_ACTIVE=5'b01110 CMD_STATE_READ_AUTOPRECHARGE=5'b00110 CMD_STATE_WRITE_AUTOPRECHARGE=5'b00010 CMD_STATE_AUTOREFRESH=5'b00011 CMD_STATE_LOAD_MODEREG=5'b01011 CMD_STATE_LOAD_MODEREG_DELAY=5'b01001 CMD_STATE_SELFREFRESH=5'b00001 CMD_STATE_SELFREFRESH_DELAY=5'b00101 CMD_STATE_BURSTSTOP_WRITE=5'b00111 CMD_STATE_BURSTSTOP_WRITE_DELAY=5'b10111 CMD_STATE_BURSTSTOP_READ=5'b10101 CMD_STATE_BURSTSTOP_READ_DELAY=5'b10001 CMD_STATE_PRECHARGE=5'b11001 CMD_STATE_PRECHARGE_DELAY=5'b11101 CMD_STATE_POWER_DOWN_MODE=5'b01101 INIT_STATE_IDLE=4'b0000 INIT_STATE_PRECHARGEALL=4'b0001 INIT_STATE_PRECHARGE_DELAY=4'b0010 INIT_STATE_AUTOREFRESH_1=4'b0011 INIT_STATE_AUTOREFRESH_DELAY_1=4'b0100 INIT_STATE_AUTOREFRESH_2=4'b0101 INIT_STATE_AUTOREFRESH_DELAY_2=4'b0110 INIT_STATE_LOAD_MODEREG=4'b0111 INIT_STATE_LOAD_MODEREG_DELAY=4'b1000 INIT_STATE_INIT_DONE=4'b1001 CPU_DATA_WIDTH=32'b00000000000000000000000000010000 SDRAM_ROW_WIDTH=32'b00000000000000000000000000001100 SDRAM_COL_WIDTH=32'b00000000000000000000000000001001 BLKADDR_MSB=32'b00000000000000000000000000001010 BLKADDR_LSB=32'b00000000000000000000000000001001 COLADDR_MSB=32'b00000000000000000000000000001000 COLADDR_LSB=32'b00000000000000000000000000000000 READ_REQ_CNT_WIDTH=32'b00000000000000000000000000001010 WIREDLY=32'b00000000000000000000000000000001 AUTO_REFRESH_COUNT=32'b00000000000000000000010111011100 Generated name = autorefresh_counter_Z2 @N:CG364 : sdram_controller.v(47) | Synthesizing module sdram_controller @W:CG133 : sdram_controller.v(247) | No assignment to power_down_reg2_i @W:CG133 : sdram_controller.v(248) | No assignment to power_down_reg3_i @W:CL246 : sdram_controller.v(180) | Input port bits 26 to 23 of i_addr[26:0] are unused @W:CL246 : sdram_controller.v(219) | Input port bits 31 to 16 of i_data[31:0] are unused @W:CL157 : sdram_controller.v(203) | *Output o_sdram_addr has undriven bits -- simulation mismatch possible. @W:CL157 : sdram_controller.v(208) | *Output o_sdram_dqm has undriven bits -- simulation mismatch possible. @N:CL201 : sdram_control_fsm.v(303) | Trying to extract state machine for register cmd_fsm_states_i Extracted state machine for register cmd_fsm_states_i State machine has 22 reachable states with original encodings of: 00000 00001 00010 00011 00101 00110 00111 01001 01011 01101 01110 01111 10000 10001 10101 10111 11000 11001 11100 11101 11110 11111 @N:CL201 : sdram_control_fsm.v(239) | Trying to extract state machine for register init_fsm_states_i Extracted state machine for register init_fsm_states_i State machine has 10 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 @W:CL247 : sdram_control_fsm.v(129) | Input port bit 22 of i_addr[22:0] is unused @END At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Mar 06 12:10:55 2014 ###########################################################] Premap Report Synopsys Lattice Technology Pre-mapping, Version maplat, Build 006R, Built Dec 13 2013 02:09:32 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09L Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Reading constraint file: G:\VEERAJ\RD\WORKING\RD1174\constraints\sdram_controller_syn.sdc Linked File: sdr_sdram_controller_scck.rpt Printing clock summary report in "G:\VEERAJ\RD\WORKING\RD1174\project\sdr_sdram_controller\sdr_sdram_controller_Implmnt\sdr_sdram_controller_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) syn_allowed_resources : blockrams=32 set on top level netlist sdram_controller Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group --------------------------------------------------------------------------------------------------------------------------------------- i_cpu_clk 100.0 MHz 10.000 declared default_clkgroup_0 lfsr_count64|o_lfsr_64_done_derived_clock 1.0 MHz 1000.000 derived (from sdram_controller|i_clk) Inferred_clkgroup_0 sdram_controller|i_clk 1.0 MHz 1000.000 inferred Inferred_clkgroup_0 ======================================================================================================================================= @W:MT529 : lfsr_count64.v(53) | Found inferred clock sdram_controller|i_clk which controls 117 sequential elements including U1.U1.lfsr_reg_i[5:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. Finished Pre Mapping Phase. @W:MO111 : sdram_controller.v(282) | Tristate driver o_sdram_dqm_1 on net o_sdram_dqm_1 has its enable tied to GND (module sdram_controller) @W:MO111 : sdram_controller.v(282) | Tristate driver o_sdram_dqm_2 on net o_sdram_dqm_2 has its enable tied to GND (module sdram_controller) @W:MO111 : sdram_controller.v(279) | Tristate driver o_sdram_addr_1 on net o_sdram_addr_1 has its enable tied to GND (module sdram_controller) @N:BN225 : | Writing default property annotation file G:\VEERAJ\RD\WORKING\RD1174\project\sdr_sdram_controller\sdr_sdram_controller_Implmnt\sdr_sdram_controller.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 69MB peak: 133MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Mar 06 12:10:59 2014 ###########################################################] Map & Optimize Report Synopsys Lattice Technology Mapper, Version maplat, Build 006R, Built Dec 13 2013 02:09:32 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09L Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) @W:MO111 : sdram_controller.v(282) | Tristate driver o_sdram_dqm_1 on net o_sdram_dqm_1 has its enable tied to GND (module sdram_controller) @W:MO111 : sdram_controller.v(282) | Tristate driver o_sdram_dqm_2 on net o_sdram_dqm_2 has its enable tied to GND (module sdram_controller) @W:MO111 : sdram_controller.v(279) | Tristate driver o_sdram_addr_1 on net o_sdram_addr_1 has its enable tied to GND (module sdram_controller) Available hyper_sources - for debug and ip models None Found @N:MT204 : | Auto Constrain mode is disabled because clocks are defined in the SDC file i_cpu_clk Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) Encoding state machine cmd_fsm_states_i[21:0] (view:work.sdram_control_fsm_Z1(verilog)) original code -> new code 00000 -> 0000000000000000000001 00001 -> 0000000000000000000010 00010 -> 0000000000000000000100 00011 -> 0000000000000000001000 00101 -> 0000000000000000010000 00110 -> 0000000000000000100000 00111 -> 0000000000000001000000 01001 -> 0000000000000010000000 01011 -> 0000000000000100000000 01101 -> 0000000000001000000000 01110 -> 0000000000010000000000 01111 -> 0000000000100000000000 10000 -> 0000000001000000000000 10001 -> 0000000010000000000000 10101 -> 0000000100000000000000 10111 -> 0000001000000000000000 11000 -> 0000010000000000000000 11001 -> 0000100000000000000000 11100 -> 0001000000000000000000 11101 -> 0010000000000000000000 11110 -> 0100000000000000000000 11111 -> 1000000000000000000000 Encoding state machine init_fsm_states_i[9:0] (view:work.sdram_control_fsm_Z1(verilog)) original code -> new code 0000 -> 0000000001 0001 -> 0000000010 0010 -> 0000000100 0011 -> 0000001000 0100 -> 0000010000 0101 -> 0000100000 0110 -> 0001000000 0111 -> 0010000000 1000 -> 0100000000 1001 -> 1000000000 @N: : sdram_control_fsm.v(737) | Found counter in view:work.sdram_control_fsm_Z1(verilog) inst read_req_cnt_i[9:0] Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 135MB peak: 136MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 135MB peak: 136MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 135MB peak: 136MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 135MB peak: 136MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 135MB peak: 136MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 135MB peak: 136MB) Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 135MB peak: 136MB) Finished technology mapping (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 141MB peak: 143MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ @N:FX1016 : sdram_controller.v(182) | SB_GB_IO inserted on the port i_clk. @N:FX1016 : sdram_controller.v(183) | SB_GB_IO inserted on the port i_rst. @N:FX1017 : | SB_GB inserted on the net i_rst_c_i. Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 136MB peak: 143MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 136MB peak: 143MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 141 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 9 instances converted, 0 sequential instances remain driven by gated/generated clocks ============================ Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------- ClockId0001 i_clk_ibuf_gb_io SB_GB_IO 141 refresh_req_i ======================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base G:\VEERAJ\RD\WORKING\RD1174\project\sdr_sdram_controller\sdr_sdram_controller_Implmnt\sdr_sdram_controller.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 136MB peak: 143MB) Writing EDIF Netlist and constraint files @W:MT558 : sdram_controller_syn.sdc(13) | Unable to locate source for clock i_cpu_clk. Clock will not be forward annotated @W:MT558 : | Unable to locate source for clock lfsr_count64|o_lfsr_64_done_derived_clock. Clock will not be forward annotated @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF I-2013.09L Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:05s; Memory used current: 137MB peak: 143MB) @W:MT420 : | Found inferred clock sdram_controller|i_clk with period 1000.00ns. Please declare a user-defined clock on object "p:i_clk" ##### START OF TIMING REPORT #####[ # Timing Report written on Thu Mar 06 12:11:08 2014 # Top view: sdram_controller Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): G:\VEERAJ\RD\WORKING\RD1174\constraints\sdram_controller_syn.sdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 987.420 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------- i_cpu_clk 100.0 MHz NA 10.000 NA NA declared default_clkgroup_0 sdram_controller|i_clk 1.0 MHz 79.5 MHz 1000.000 12.580 987.420 inferred Inferred_clkgroup_0 =============================================================================================================================== @W:MT548 : sdram_controller_syn.sdc(13) | Source for clock i_cpu_clk not found in netlist Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------- sdram_controller|i_clk sdram_controller|i_clk | 1000.000 987.420 | No paths - | No paths - | No paths - ======================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: sdram_controller|i_clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------- U0.clk_count_i[0] sdram_controller|i_clk SB_DFF Q clk_count_i[0] 0.796 987.420 U0.clk_count_i[1] sdram_controller|i_clk SB_DFF Q clk_count_i[1] 0.796 987.420 U0.clk_count_i[3] sdram_controller|i_clk SB_DFF Q clk_count_i[3] 0.796 987.431 U0.clk_count_i[2] sdram_controller|i_clk SB_DFF Q clk_count_i[2] 0.796 987.493 U0.cmd_fsm_states_i[7] sdram_controller|i_clk SB_DFFR Q cmd_fsm_states_i[7] 0.796 987.637 U0.cmd_fsm_states_i[12] sdram_controller|i_clk SB_DFFR Q cmd_fsm_states_i[12] 0.796 987.710 U0.cmd_fsm_states_i[16] sdram_controller|i_clk SB_DFFR Q cmd_fsm_states_i[16] 0.796 987.741 U0.cmd_fsm_states_i[17] sdram_controller|i_clk SB_DFFR Q cmd_fsm_states_i[17] 0.796 987.834 U0.o_init_done sdram_controller|i_clk SB_DFFR Q o_init_done_c 0.796 989.360 U0.cmd_fsm_states_i[1] sdram_controller|i_clk SB_DFFR Q cmd_fsm_states_i[1] 0.796 989.380 ======================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------- U0.clk_count_i[0] sdram_controller|i_clk SB_DFF D clk_count_i_0[0] 999.845 987.420 U0.clk_count_i[1] sdram_controller|i_clk SB_DFF D clk_count_i_0[1] 999.845 987.420 U0.clk_count_i[2] sdram_controller|i_clk SB_DFF D clk_count_i_0[2] 999.845 987.420 U0.clk_count_i[3] sdram_controller|i_clk SB_DFF D clk_count_i_0[3] 999.845 987.420 U0.cmd_fsm_states_i[0] sdram_controller|i_clk SB_DFFS D cmd_fsm_states_i_RNO[0] 999.845 987.420 U0.read_done_i sdram_controller|i_clk SB_DFFR D read_done_i_0 999.845 989.256 U0.write_done_i sdram_controller|i_clk SB_DFFR D write_done_i_0 999.845 989.256 U0.o_sdram_addr_1[10] sdram_controller|i_clk SB_DFFE D o_sdram_addr_7_0_i[10] 999.845 989.401 U0.o_ack sdram_controller|i_clk SB_DFFR D o_ack 999.845 989.422 U0.cmd_fsm_states_i[11] sdram_controller|i_clk SB_DFFR D cmd_fsm_states_i_RNO[11] 999.845 991.217 ============================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.155 + Clock delay at ending point: 0.000 (ideal) = Required time: 999.845 - Propagation time: 12.425 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 987.420 Number of logic level(s): 5 Starting point: U0.clk_count_i[0] / Q Ending point: U0.clk_count_i[0] / D The start point is clocked by sdram_controller|i_clk [rising] on pin C The end point is clocked by sdram_controller|i_clk [rising] on pin C Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- U0.clk_count_i[0] SB_DFF Q Out 0.796 0.796 - clk_count_i[0] Net - - 1.599 - 10 U0.clk_count_i_RNICEBA_0[2] SB_LUT4 I0 In - 2.395 - U0.clk_count_i_RNICEBA_0[2] SB_LUT4 O Out 0.661 3.056 - N_67 Net - - 1.371 - 3 U0.cmd_fsm_states_i_RNI7RGR[21] SB_LUT4 I0 In - 4.427 - U0.cmd_fsm_states_i_RNI7RGR[21] SB_LUT4 O Out 0.569 4.996 - N_176_1 Net - - 1.371 - 2 U0.clk_count_i_RNICBAP2[3] SB_LUT4 I1 In - 6.367 - U0.clk_count_i_RNICBAP2[3] SB_LUT4 O Out 0.589 6.956 - reset_clk_counter_i_0_i_0_1_0 Net - - 1.371 - 1 U0.init_fsm_states_i_RNIM3PV5[9] SB_LUT4 I1 In - 8.327 - U0.init_fsm_states_i_RNIM3PV5[9] SB_LUT4 O Out 0.558 8.885 - init_fsm_states_i_RNIM3PV5[9] Net - - 1.371 - 4 U0.clk_count_i_RNO[0] SB_LUT4 I0 In - 10.256 - U0.clk_count_i_RNO[0] SB_LUT4 O Out 0.661 10.918 - clk_count_i_0[0] Net - - 1.507 - 1 U0.clk_count_i[0] SB_DFF D In - 12.425 - ================================================================================================== Total path delay (propagation time + setup) of 12.580 is 3.990(31.7%) logic and 8.590(68.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for sdram_controller Mapping to part: ice40lp8kcm225 Cell usage: GND 5 uses SB_CARRY 9 uses SB_DFF 20 uses SB_DFFE 20 uses SB_DFFER 20 uses SB_DFFES 26 uses SB_DFFR 53 uses SB_DFFS 2 uses SB_GB 1 use VCC 5 uses SB_LUT4 188 uses I/O ports: 167 I/O primitives: 130 SB_GB_IO 2 uses SB_IO 128 uses I/O Register bits: 0 Register bits not including I/Os: 141 (1%) Total load per clock: sdram_controller|i_clk: 1 Mapping Summary: Total LUTs: 188 (2%) Distribution of All Consumed LUTs = LUT4 Distribution of All Consumed Luts 188 = 188 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:06s; Memory used current: 55MB peak: 143MB) Process took 0h:00m:08s realtime, 0h:00m:06s cputime # Thu Mar 06 12:11:08 2014 ###########################################################]