Project Settings
Project Name sdr_sdram_controller_syn Implementation Name sdr_sdram_controller_Implmnt
Top Module [auto] Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 10000 Disable I/O Insertion 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
Compile InputComplete 9 14 0 - 0m:05s - 3/6/2014
12:10:55 PM
PremapComplete 3 4 0 0m:01s 0m:01s 133MB 3/6/2014
12:10:59 PM
Map & OptimizeComplete 12 8 0 0m:06s 0m:08s 143MB 3/6/2014
12:11:08 PM

Area Summary
PADS 167 FLOPS 141
RAMS (v_ram) 0 CARRYS 9
LUTS (total_luts) 188

Timing Summary
Clock NameReq FreqEst FreqSlack
i_cpu_clk100.0 MHzNANA
sdram_controller|i_clk1.0 MHz79.5 MHz987.420

Optimizations Summary
Combined Clock Conversion 1 / 0