Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:MF827 :  | No constraint file specified. 
Linked File: calculator_impl1_scck.rpt
Printing clock  summary report in "C:\Users\TEST\Desktop\calculator_fpga_mico8\impl1\calculator_impl1_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
@W:BN132 : cap1298_i2c.v(94) | Removing sequential instance cap1298_top_u.cap1298_i2c_u3.data_wr[6] because it is equivalent to instance cap1298_top_u.cap1298_i2c_u3.data_wr[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : cap1298_top.v(130) | Removing sequential instance operate_status_r[8:0] (in view: work.cap1298_top(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : cap1298_top.v(130) | Removing sequential instance operate_status[8] (in view: work.cap1298_top(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : cap1298_top.v(130) | Removing sequential instance operate_status[7] (in view: work.cap1298_top(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : cap1298_top.v(130) | Removing sequential instance operate_status[6] (in view: work.cap1298_top(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : cap1298_top.v(130) | Removing sequential instance operate_status[5] (in view: work.cap1298_top(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : cap1298_top.v(130) | Removing sequential instance operate_status[4] (in view: work.cap1298_top(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : cap1298_top.v(130) | Removing sequential instance operate_status[3] (in view: work.cap1298_top(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : cap1298_top.v(130) | Removing sequential instance operate_status[2] (in view: work.cap1298_top(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : cap1298_top.v(130) | Removing sequential instance operate_status[1] (in view: work.cap1298_top(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : cap1298_top.v(130) | Removing sequential instance operate_status[0] (in view: work.cap1298_top(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : cap1298_top.v(68) | Removing sequential instance key_operate[8:0] (in view: work.cap1298_top(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=10  set on top level netlist calculator

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)



Clock Summary
*****************

Start                                      Requested     Requested     Clock                                Clock                   Clock
Clock                                      Frequency     Period        Type                                 Group                   Load 
-----------------------------------------------------------------------------------------------------------------------------------------
calculator|clk_in                          1.0 MHz       1000.000      inferred                             Inferred_clkgroup_0     101  
cap1298_i2c_0|clk_200khz_derived_clock     1.0 MHz       1000.000      derived (from calculator|clk_in)     Inferred_clkgroup_0     63   
cap1298_i2c_1|clk_200khz_derived_clock     1.0 MHz       1000.000      derived (from calculator|clk_in)     Inferred_clkgroup_0     63   
cap1298_i2c_2|clk_200khz_derived_clock     1.0 MHz       1000.000      derived (from calculator|clk_in)     Inferred_clkgroup_0     63   
=========================================================================================================================================

@W:MT529 : cap1298_i2c.v(61) | Found inferred clock calculator|clk_in which controls 101 sequential elements including cap1298_top_u.cap1298_i2c_u1.cnt_200khz[5:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 142MB)

Encoding state machine state[9:0] (in view: work.cap1298_i2c_2(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
Encoding state machine state[9:0] (in view: work.cap1298_i2c_1(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
Encoding state machine state[9:0] (in view: work.cap1298_i2c_0(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
Encoding state machine state[2:0] (in view: work.calculator(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10
None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 143MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 57MB peak: 143MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Sep 30 00:22:16 2017

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