Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.8.0.115.3

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
Sat Sep 30 17:25:44 2017


Command Line:  synthesis -f calculator_impl1_lattice.synproj -gui -msgset C:/Users/TEST/Desktop/calculator_fpga_mico8/promote.xml 

Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is CSBGA132.
The -d option is LCMXO2-4000HC.
Using package CSBGA132.
Using performance grade 4.
                                                          

##########################################################

### Lattice Family : MachXO2

### Device  : LCMXO2-4000HC

### Package : CSBGA132

### Speed   : 4

##########################################################

                                                          

Optimization goal = Balanced
Top-level module name = calculator.
Target frequency = 1.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Users/TEST/Desktop/calculator_fpga_mico8 (searchpath added)
-p C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data (searchpath added)
-p C:/Users/TEST/Desktop/calculator_fpga_mico8/impl1 (searchpath added)
-p C:/Users/TEST/Desktop/calculator_fpga_mico8 (searchpath added)
Verilog design file = C:/Users/TEST/Desktop/calculator_fpga_mico8/source/cap1298_i2c.v
Verilog design file = C:/Users/TEST/Desktop/calculator_fpga_mico8/source/cap1298_top.v
Verilog design file = C:/Users/TEST/Desktop/calculator_fpga_mico8/source/define_reg.v
Verilog design file = C:/Users/TEST/Desktop/calculator_fpga_mico8/source/display.v
Verilog design file = C:/Users/TEST/Desktop/calculator_fpga_mico8/source/calculator.v
Verilog design file = C:/Users/TEST/Desktop/calculator_fpga_mico8/source/Uart_Tx.v
Verilog design file = C:/Users/TEST/Desktop/calculator_fpga_mico8/source/Baud.v
Verilog design file = C:/Users/TEST/Desktop/calculator_fpga_mico8/source/compute.v
Verilog design file = C:/Users/TEST/Desktop/calculator_fpga_mico8/source/bin_bcd.v
NGD file = calculator_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/users/test/desktop/calculator_fpga_mico8/source/cap1298_i2c.v. VERI-1482
INFO - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/cap1298_i2c.v(18): analyzing included file c:/users/test/desktop/calculator_fpga_mico8/source/define_reg.v. VERI-1328
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/cap1298_i2c.v(51): potential always loop found. VERI-1931
Analyzing Verilog file c:/users/test/desktop/calculator_fpga_mico8/source/cap1298_top.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/calculator_fpga_mico8/source/define_reg.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/calculator_fpga_mico8/source/display.v. VERI-1482
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/display.v(40): potential always loop found. VERI-1931
Analyzing Verilog file c:/users/test/desktop/calculator_fpga_mico8/source/calculator.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/calculator_fpga_mico8/source/uart_tx.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/calculator_fpga_mico8/source/baud.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/calculator_fpga_mico8/source/compute.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/calculator_fpga_mico8/source/bin_bcd.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): calculator
INFO - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/calculator.v(1): compiling module calculator. VERI-1018
INFO - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/cap1298_top.v(18): compiling module cap1298_top. VERI-1018
INFO - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/cap1298_i2c.v(20): compiling module cap1298_i2c. VERI-1018
INFO - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/display.v(18): compiling module display. VERI-1018
INFO - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/compute.v(1): compiling module compute. VERI-1018
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/compute.v(90): expression size 32 truncated to fit in target size 16. VERI-1209
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/compute.v(92): expression size 32 truncated to fit in target size 16. VERI-1209
INFO - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/bin_bcd.v(8): compiling module bin_bcd. VERI-1018
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/compute.v(258): actual bit length 16 differs from formal bit length 12 for port binary. VERI-1330
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/compute.v(34): net bcd_data_reg[3][7] does not have a driver. VDB-1002
INFO - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/baud.v(18): compiling module Baud. VERI-1018
INFO - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/uart_tx.v(18): compiling module Uart_Tx. VERI-1018
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/uart_tx.v(43): expression size 32 truncated to fit in target size 1. VERI-1209
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
Package Status:                     Final          Version 1.44.
Top-level module name = calculator.
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/compute.v(34): net bcd_data_reg[3][7] does not have a driver. VDB-1002
######## Missing driver on net lcd_rst_out. Patching with GND.
######## Missing driver on net lcd_cs_out. Patching with GND.
######## Missing driver on net lcd_dc_out. Patching with GND.
######## Missing driver on net lcd_clk_out. Patching with GND.
######## Missing driver on net lcd_data_out. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[3][7]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[3][6]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[3][5]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[3][4]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[3][3]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[3][2]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[3][1]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[3][0]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[2][7]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[2][6]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[2][5]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[2][4]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[2][3]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[2][2]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[2][1]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[2][0]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[1][7]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[1][6]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[1][5]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[1][4]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[1][3]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[1][2]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[1][1]. Patching with GND.
######## Missing driver on net \compute_u/bcd_data_reg[1][0]. Patching with GND.
INFO - synthesis: Extracted state machine for register 'txstate' with one-hot encoding
State machine has 5 reachable states with original encodings of:

 000 

 001 

 010 

 011 

 100 

original encoding -> new encoding (one-hot encoding)

 000 -> 00001

 001 -> 00010

 010 -> 00100

 011 -> 01000

 100 -> 10000

INFO - synthesis: Extracted state machine for register '\compute_u/state' with one-hot encoding
State machine has 11 reachable states with original encodings of:

 0000 

 0001 

 0010 

 0011 

 0100 

 0101 

 0110 

 0111 

 1000 

 1001 

 1010 

original encoding -> new encoding (one-hot encoding)

 0000 -> 00000000001

 0001 -> 00000000010

 0010 -> 00000000100

 0011 -> 00000001000

 0100 -> 00000010000

 0101 -> 00000100000

 0110 -> 00001000000

 0111 -> 00010000000

 1000 -> 00100000000

 1001 -> 01000000000

 1010 -> 10000000000




WARNING - synthesis: Bit 0 of Register txstate_FSM is stuck at Zero
WARNING - synthesis: Bit 1 of Register txstate_FSM is stuck at Zero
WARNING - synthesis: Bit 2 of Register txstate_FSM is stuck at Zero
WARNING - synthesis: Bit 0 of Register \compute_u/state_FSM is stuck at Zero
WARNING - synthesis: Bit 1 of Register \compute_u/state_FSM is stuck at Zero
WARNING - synthesis: Bit 2 of Register \compute_u/state_FSM is stuck at Zero
WARNING - synthesis: Bit 3 of Register \compute_u/state_FSM is stuck at Zero
WARNING - synthesis: Bit 4 of Register \compute_u/state_FSM is stuck at Zero
WARNING - synthesis: Bit 9 of Register \Uart_Tx_u/tx_data_r is stuck at Zero
Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Analyzing Verilog file mult_16u_16u.v. VERI-1482
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/compute.v(114): input port a[15] is not connected on this instance. VDB-1013
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/cap1298_i2c.v(275): Register \cap1298_top_u/cap1298_i2c_u1/state_back_i0_i2 is stuck at Zero. VDB-5013
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/compute.v(253): Register \compute_u/bcd_data_reg[0][4]_200 is stuck at One. VDB-5014
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/compute.v(253): Register \compute_u/bcd_data_reg[0][6]_198 is stuck at Zero. VDB-5013
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/calculator.v(172): Register data_out_reg_i0_i7 is stuck at Zero. VDB-5013
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/uart_tx.v(62): Register \Uart_Tx_u/tx_data_r__i8 is stuck at Zero. VDB-5013
WARNING - synthesis: c:/users/test/desktop/calculator_fpga_mico8/source/cap1298_top.v(210): Register \cap1298_top_u/cnt_i0_i3 is stuck at Zero. VDB-5013
Duplicate register/latch removal. \compute_u/value1__i0 is a one-to-one match with \compute_u/value1__rep_66_i1.
Duplicate register/latch removal. \compute_u/value1__i1 is a one-to-one match with \compute_u/value1__rep_66_i2.
Duplicate register/latch removal. \compute_u/value1__i2 is a one-to-one match with \compute_u/value1__rep_66_i3.
Duplicate register/latch removal. \compute_u/value1__i3 is a one-to-one match with \compute_u/value1__rep_66_i4.
Duplicate register/latch removal. \compute_u/value1__i4 is a one-to-one match with \compute_u/value1__rep_66_i5.
Duplicate register/latch removal. \compute_u/value1__i5 is a one-to-one match with \compute_u/value1__rep_66_i6.
Duplicate register/latch removal. \compute_u/value1__i6 is a one-to-one match with \compute_u/value1__rep_66_i7.
Duplicate register/latch removal. \compute_u/value1__i7 is a one-to-one match with \compute_u/value1__rep_66_i8.
Duplicate register/latch removal. \compute_u/value1__i8 is a one-to-one match with \compute_u/value1__rep_66_i9.
Duplicate register/latch removal. \compute_u/value1__i9 is a one-to-one match with \compute_u/value1__rep_66_i10.
Duplicate register/latch removal. \compute_u/value1__i10 is a one-to-one match with \compute_u/value1__rep_66_i11.
Duplicate register/latch removal. \compute_u/value1__i11 is a one-to-one match with \compute_u/value1__rep_66_i12.
Duplicate register/latch removal. \compute_u/value1__i12 is a one-to-one match with \compute_u/value1__rep_66_i13.
Duplicate register/latch removal. \compute_u/value1__i13 is a one-to-one match with \compute_u/value1__rep_66_i14.
Duplicate register/latch removal. \compute_u/value1__i14 is a one-to-one match with \compute_u/value1__rep_66_i15.
Duplicate register/latch removal. \compute_u/value1__i15 is a one-to-one match with \compute_u/value1__rep_66_i16.
GSR instance connected to net rst_n_in_c.
Duplicate register/latch removal. \cap1298_top_u/cap1298_i2c_u3/cnt_read_i0_i3 is a one-to-one match with \cap1298_top_u/cap1298_i2c_u3/cnt_read_i0_i4.
Applying 1.000000 MHz constraint to all clocks

WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in calculator_drc.log.
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
WARNING - synthesis: logical net 'uart_in' has no load.
WARNING - synthesis: input pad net 'uart_in' has no legal load.
WARNING - synthesis: DRC complete with 2 warnings.
All blocks are expanded and NGD expansion is successful.
Writing NGD file calculator_impl1.ngd.

################### Begin Area Report (calculator)######################
Number of register bits => 426 of 4635 (9 % )
AND2 => 8
BB => 3
CCU2D => 360
FADD2B => 43
FD1P3AX => 178
FD1P3AY => 8
FD1P3IX => 115
FD1P3JX => 19
FD1S3AX => 31
FD1S3AY => 45
FD1S3IX => 30
GSR => 1
IB => 2
L6MUX21 => 3
LUT4 => 1253
MULT2 => 36
OB => 35
PFUMX => 77
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 4
  Net : clk_in_c, loads : 417
  Net : cap1298_top_u/cap1298_i2c_u1/clk_200khz, loads : 14
  Net : cap1298_top_u/cap1298_i2c_u3/clk_200khz, loads : 12
  Net : cap1298_top_u/cap1298_i2c_u2/clk_200khz, loads : 12
Clock Enable Nets
Number of Clock Enables: 132
Top 10 highest fanout Clock Enables:
  Net : compute_u/clk_in_c_enable_259, loads : 16
  Net : compute_u/clk_in_c_enable_167, loads : 16
  Net : compute_u/clk_in_c_enable_82, loads : 16
  Net : compute_u/clk_in_c_enable_256, loads : 8
  Net : cap1298_top_u/cap1298_i2c_u1/clk_in_c_enable_57, loads : 8
  Net : cap1298_top_u/cap1298_i2c_u3/clk_in_c_enable_117, loads : 8
  Net : cap1298_top_u/cap1298_i2c_u3/clk_in_c_enable_293, loads : 8
  Net : cap1298_top_u/cap1298_i2c_u2/clk_in_c_enable_215, loads : 8
  Net : cap1298_top_u/cap1298_i2c_u2/clk_in_c_enable_100, loads : 8
  Net : clk_in_c_enable_287, loads : 7
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : compute_u/value2_0, loads : 71
  Net : cap1298_top_u/cap1298_i2c_u1/state_0, loads : 62
  Net : cap1298_top_u/cap1298_i2c_u2/state_0, loads : 57
  Net : cap1298_top_u/cap1298_i2c_u1/state_2, loads : 54
  Net : cap1298_top_u/cap1298_i2c_u3/state_0, loads : 54
  Net : compute_u/value2_2, loads : 53
  Net : compute_u/value2_1, loads : 53
  Net : cap1298_top_u/cap1298_i2c_u3/state_2, loads : 51
  Net : cap1298_top_u/cap1298_i2c_u2/state_2, loads : 51
  Net : compute_u/value2_3, loads : 51
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk3 [get_nets                          |             |             |
\cap1298_top_u/cap1298_i2c_u2/clk_200khz|             |             |
]                                       |            -|            -|     0  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk2 [get_nets clk_200khz]              |            -|            -|     0  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk1 [get_nets clk_200khz_adj_1156]     |            -|            -|     0  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk0 [get_nets clk_in_c]                |    1.000 MHz|    9.459 MHz|   153  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.


Peak Memory Usage: 167.375  MB

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Elapsed CPU time for LSE flow : 20.530  secs
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