Project Settings
Project Name proj_1 Implementation Name impl1
Top Module cap1298_top Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 1000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 Clock Conversion 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 13 32 0 - 0m:02s - 2017/11/1
16:43:33
(premap)Complete 2 3 0 0m:01s 0m:01s 142MB 2017/11/1
16:43:37
(fpga_mapper)Complete 19 1 0 0m:06s 0m:06s 184MB 2017/11/1
16:43:43
Multi-srs Generator Complete2017/11/1
16:43:34

Area Summary
Register bits 259 I/O cells 34
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 619

Timing Summary
Clock NameReq FreqEst FreqSlack
cap1298_top|clk_in1.0 MHz104.9 MHz990.463

Optimizations Summary
Combined Clock Conversion 1 / 0