Setting log file to 'C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/impl1/hdla_gen_hierarchy.html'. Starting: parse design source files (VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v (VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/define_reg.v (VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/display.v WARNING - C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/display.v(28,1-40,5) (VERI-1931) potential always loop found (VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/cap1298_i2c.v INFO - C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/cap1298_i2c.v(18,10-18,24) (VERI-1328) analyzing included file C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/define_reg.v (VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/cap1298_top.v INFO - C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/cap1298_top.v(18,8-18,19) (VERI-1018) compiling module cap1298_top INFO - C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/cap1298_top.v(18,1-185,10) (VERI-9000) elaborating module 'cap1298_top' INFO - C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/cap1298_i2c.v(20,1-279,10) (VERI-9000) elaborating module 'cap1298_i2c_uniq_1' INFO - C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/cap1298_i2c.v(20,1-279,10) (VERI-9000) elaborating module 'cap1298_i2c_uniq_2' INFO - C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/cap1298_i2c.v(20,1-279,10) (VERI-9000) elaborating module 'cap1298_i2c_uniq_3' INFO - C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/source/display.v(18,1-79,10) (VERI-9000) elaborating module 'display_uniq_1' Done: design load finished with (0) errors, and (1) warnings