Setting log file to 'C:/Users/TEST/Desktop/calculator_fpga_mico8/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga_mico8/source/cap1298_i2c.v
INFO - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/cap1298_i2c.v(18,10-18,24) (VERI-1328) analyzing included file C:/Users/TEST/Desktop/calculator_fpga_mico8/source/define_reg.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga_mico8/source/cap1298_top.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga_mico8/source/define_reg.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga_mico8/source/display.v
WARNING - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/display.v(28,1-40,5) (VERI-1931) potential always loop found
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga_mico8/source/calculator.v
WARNING - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/calculator.v(44,19-44,29) (VERI-1875) identifier uart_tx_rx is used before its declaration
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga_mico8/source/Uart_Tx.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga_mico8/source/Baud.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga_mico8/source/compute.v
WARNING - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/compute.v(219,5-219,15) (VERI-1372) redeclaration of ansi port uart_tx_en is not allowed
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga_mico8/source/bin_bcd.v
INFO - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/calculator.v(1,8-1,18) (VERI-1018) compiling module calculator
INFO - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/calculator.v(1,1-137,10) (VERI-9000) elaborating module 'calculator'
INFO - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/cap1298_top.v(18,1-225,10) (VERI-9000) elaborating module 'cap1298_top_uniq_1'
INFO - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/compute.v(1,1-326,10) (VERI-9000) elaborating module 'compute_uniq_1'
INFO - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/Baud.v(18,1-51,10) (VERI-9000) elaborating module 'Baud_uniq_1'
INFO - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/Uart_Tx.v(18,1-93,10) (VERI-9000) elaborating module 'Uart_Tx_uniq_1'
INFO - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/cap1298_i2c.v(20,1-279,10) (VERI-9000) elaborating module 'cap1298_i2c_uniq_1'
INFO - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/display.v(18,1-79,10) (VERI-9000) elaborating module 'display_uniq_1'
INFO - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/bin_bcd.v(8,1-66,10) (VERI-9000) elaborating module 'bin_bcd_uniq_1'
WARNING - C:/Users/TEST/Desktop/calculator_fpga_mico8/source/compute.v(215,1-215,20) (VERI-1330) actual bit length 16 differs from formal bit length 12 for port binary
Done: design load finished with (0) errors, and (4) warnings