Lattice Mapping Report File for Design Module 'calculator_lcd'



Design Information

Command line:   map -a MachXO2 -p LCMXO2-4000HC -t CSBGA132 -s 4 -oc Commercial
     calculator_lcd_impl1.ngd -o calculator_lcd_impl1_map.ncd -pr
     calculator_lcd_impl1.prf -mp calculator_lcd_impl1.mrp -lpf C:/Users/TEST/De
     sktop/calculator_fpga/calculator_lcd/impl1/calculator_lcd_impl1.lpf -lpf
     C:/Users/TEST/Desktop/calculator_fpga/calculator_lcd/calculator_lcd.lpf -c
     0 -gui -msgset
     C:/Users/TEST/Desktop/calculator_fpga/calculator_lcd/promote.xml 
Target Vendor:  LATTICE
Target Device:  LCMXO2-4000HCCSBGA132
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond (64-bit) 3.8.0.115.3
Mapped on:  11/01/17  17:02:37


Design Summary
   Number of registers:     83 out of  4635 (2%)
      PFU registers:           83 out of  4320 (2%)
      PIO registers:            0 out of   315 (0%)
   Number of SLICEs:       121 out of  2160 (6%)
      SLICEs as Logic/ROM:    121 out of  2160 (6%)
      SLICEs as RAM:            0 out of  1620 (0%)
      SLICEs as Carry:         27 out of  2160 (1%)
   Number of LUT4s:        241 out of  4320 (6%)
      Number used as logic LUTs:        187
      Number used as distributed RAM:     0
      Number used as ripple logic:       54
      Number used as shift registers:     0
   Number of PIO sites used: 7 + 4(JTAG) out of 105 (10%)
   Number of block RAMs:  0 out of 10 (0%)
   Number of GSRs:  1 out of 1 (100%)
   EFB used :       No
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 6 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 2 (0%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  1
     Net clk_c: 56 loads, 56 rising, 0 falling (Driver: PIO clk )

   Number of Clock Enables:  15
     Net clk_c_enable_15: 3 loads, 3 LSLICEs
     Net clk_c_enable_4: 1 loads, 1 LSLICEs
     Net clk_c_enable_26: 2 loads, 2 LSLICEs
     Net clk_c_enable_58: 8 loads, 8 LSLICEs
     Net clk_c_enable_57: 4 loads, 4 LSLICEs
     Net clk_c_enable_8: 1 loads, 1 LSLICEs
     Net clk_c_enable_55: 6 loads, 6 LSLICEs
     Net clk_c_enable_13: 2 loads, 2 LSLICEs
     Net rst_n_c: 1 loads, 1 LSLICEs
     Net clk_c_enable_63: 5 loads, 5 LSLICEs
     Net clk_c_enable_62: 2 loads, 2 LSLICEs
     Net clk_c_enable_47: 1 loads, 1 LSLICEs
     Net clk_c_enable_34: 1 loads, 1 LSLICEs
     Net clk_c_enable_36: 1 loads, 1 LSLICEs
     Net clk_c_enable_60: 6 loads, 6 LSLICEs
   Number of LSRs:  7
     Net n6016: 9 loads, 9 LSLICEs
     Net n7664: 8 loads, 8 LSLICEs
     Net n6045: 4 loads, 4 LSLICEs
     Net n8221: 1 loads, 1 LSLICEs
     Net n8050: 1 loads, 1 LSLICEs
     Net n6525: 5 loads, 5 LSLICEs
     Net clk_div_state_1: 1 loads, 1 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net data_state_0: 31 loads
     Net data_state_1: 28 loads
     Net data_state_cnt_4: 26 loads
     Net data_state_cnt_3: 23 loads
     Net data_state_cnt_2: 21 loads
     Net data_state_2: 20 loads
     Net data_state_cnt_0: 20 loads
     Net data_state_cnt_1: 16 loads
     Net data_state_cnt_5: 16 loads
     Net n3792: 13 loads




   Number of warnings:  0
   Number of errors:    0
     




Design Errors/Warnings

   No errors or warnings present.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+

| lcd_data_out        | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| clk                 | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| rst_n               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| lcd_clk_out         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| lcd_dc_out          | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| lcd_cs_n_out        | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| lcd_rst_n_out       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+



Removed logic

Block i4365 undriven or does not drive anything - clipped.
Signal GND_net undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal delay_cnt_1065_1066_add_4_1/S0 undriven or does not drive anything -
     clipped.
Signal delay_cnt_1065_1066_add_4_1/CI undriven or does not drive anything -
     clipped.
Signal temp_cnt_1064_add_4_9/CO undriven or does not drive anything - clipped.
Signal clk_cnt_1067_add_4_17/S1 undriven or does not drive anything - clipped.
Signal clk_cnt_1067_add_4_17/CO undriven or does not drive anything - clipped.
Signal data_state_cnt_1063_add_4_1/S0 undriven or does not drive anything -
     clipped.
Signal data_state_cnt_1063_add_4_1/CI undriven or does not drive anything -
     clipped.
Signal data_state_cnt_1063_add_4_9/S1 undriven or does not drive anything -
     clipped.
Signal data_state_cnt_1063_add_4_9/CO undriven or does not drive anything -
     clipped.
Signal delay_cnt_1065_1066_add_4_15/S1 undriven or does not drive anything -
     clipped.
Signal delay_cnt_1065_1066_add_4_15/CO undriven or does not drive anything -
     clipped.
Signal clk_cnt_1067_add_4_1/S0 undriven or does not drive anything - clipped.
Signal clk_cnt_1067_add_4_1/CI undriven or does not drive anything - clipped.
Signal temp_cnt_1064_add_4_1/S0 undriven or does not drive anything - clipped.
Signal temp_cnt_1064_add_4_1/CI undriven or does not drive anything - clipped.
Block i1 was optimized away.



Memory Usage


     



GSR Usage
---------

GSR Component:

   The Global Set Reset (GSR) resource has been used to implement a global reset
        of the design. The reset signal used for GSR control is 'rst_n_c'.
        

     GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.
        

     Components with disabled GSR Property
-------------------------------------

     These components have the GSR property set to DISABLED. The components will
     not respond to the reset signal 'rst_n_c' via the GSR component.

     Type and number of components of the type: 
   Register = 52 

     Type and instance name of component: 
   Register : shift_cnt_1068__i3
   Register : shift_cnt_1068__i2
   Register : shift_cnt_1068__i1
   Register : char_reg__0__i1
   Register : temp__i1
   Register : delay_cnt_1065_1066__i6
   Register : cmd_reg_i0_i4
   Register : cmd_reg_i0_i3
   Register : data_state_back__i1
   Register : cmd_reg_i0_i0
   Register : data_state_back__i2
   Register : temp_cnt_1064__i3
   Register : shift_cnt_1068__i0
   Register : temp_cnt_1064__i4
   Register : temp_cnt_1064__i6
   Register : delay_cnt_1065_1066__i7
   Register : delay_cnt_1065_1066__i8
   Register : delay_cnt_1065_1066__i9
   Register : delay_cnt_1065_1066__i10
   Register : delay_cnt_1065_1066__i11
   Register : delay_cnt_1065_1066__i12
   Register : delay_cnt_1065_1066__i13
   Register : temp__i3
   Register : delay_cnt_1065_1066__i14
   Register : temp_cnt_1064__i7
   Register : temp_cnt_1064__i8
   Register : delay_cnt_1065_1066__i2
   Register : delay_cnt_1065_1066__i3
   Register : data_reg__i7
   Register : lcd_data_out_191
   Register : delay_cnt_1065_1066__i4
   Register : lcd_rst_n_out_186
   Register : data_reg__i6
   Register : data_reg__i5
   Register : data_reg__i4
   Register : data_reg__i3

   Register : delay_cnt_1065_1066__i5
   Register : data_reg__i2
   Register : data_reg__i1
   Register : cmd_reg_i0_i7
   Register : cmd_reg_i0_i6
   Register : cmd_reg_i0_i2
   Register : lcd_dc_out_193
   Register : cmd_reg_i0_i1
   Register : temp_cnt_1064__i1
   Register : clk_div_179
   Register : temp_cnt_1064__i2
   Register : cmd_reg_i0_i5
   Register : delay_cnt_1065_1066__i1
   Register : temp_cnt_1064__i5
   Register : data_reg__i0
   Register : temp_cnt_1064__i0

     Components with synchronous local reset also reset by asynchronous GSR
----------------------------------------------------------------------

     These components have the GSR property set to ENABLED and the local reset
     is synchronous. The components will respond to the synchronous local reset
     and to the unrelated asynchronous reset signal 'rst_n_c' via the GSR
     component.

     Type and number of components of the type: 
   Register = 22 

     Type and instance name of component: 
   Register : clk_cnt_1067__i15
   Register : data_state_cnt_1063__i2
   Register : clk_cnt_1067__i14
   Register : clk_cnt_1067__i13
   Register : clk_cnt_1067__i12
   Register : clk_cnt_1067__i11
   Register : clk_cnt_1067__i10
   Register : clk_cnt_1067__i9
   Register : clk_cnt_1067__i8
   Register : clk_cnt_1067__i7
   Register : clk_cnt_1067__i6
   Register : clk_cnt_1067__i5
   Register : clk_cnt_1067__i4
   Register : clk_cnt_1067__i0
   Register : clk_cnt_1067__i3
   Register : clk_cnt_1067__i2
   Register : clk_cnt_1067__i1
   Register : clk_div_state_i1
   Register : data_state_cnt_1063__i4
   Register : data_state_cnt_1063__i6
   Register : data_state_cnt_1063__i7
   Register : data_state_cnt_1063__i1



Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs  

   Total REAL Time: 0 secs  
   Peak Memory Usage: 50 MB
        
























































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