#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul  4 2016
#install: C:\lscc\diamond\3.8_x64\synpbase
#OS: Windows 7 6.1
#Hostname: TEST-PC

# Thu Oct 26 14:30:50 2017

#Implementation: impl1

Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Synopsys Verilog Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\TEST\Desktop\calculator_fpga_mico8\source\cap1298_i2c.v" (library work)
@I:"C:\Users\TEST\Desktop\calculator_fpga_mico8\source\cap1298_i2c.v":"C:\Users\TEST\Desktop\calculator_fpga_mico8\source\define_reg.v" (library work)
@I::"C:\Users\TEST\Desktop\calculator_fpga_mico8\source\cap1298_top.v" (library work)
@I::"C:\Users\TEST\Desktop\calculator_fpga_mico8\source\display.v" (library work)
@I::"C:\Users\TEST\Desktop\calculator_fpga_mico8\source\calculator.v" (library work)
@I::"C:\Users\TEST\Desktop\calculator_fpga_mico8\source\Uart_Tx.v" (library work)
@I::"C:\Users\TEST\Desktop\calculator_fpga_mico8\source\Baud.v" (library work)
@I::"C:\Users\TEST\Desktop\calculator_fpga_mico8\source\compute.v" (library work)
@I::"C:\Users\TEST\Desktop\calculator_fpga_mico8\source\bin_bcd.v" (library work)
Verilog syntax check successful!
File C:\Users\TEST\Desktop\calculator_fpga_mico8\source\compute.v changed - recompiling
Selecting top level module calculator
@N:CG364 : cap1298_i2c.v(20) | Synthesizing module cap1298_i2c in library work.

@N:CG179 : cap1298_i2c.v(243) | Removing redundant assignment.
@W:CL169 : cap1298_i2c.v(85) | Pruning unused register init_num[2:0]. Make sure that there are no unused intermediate registers.
@A:CL282 : cap1298_i2c.v(85) | Feedback mux created for signal data_wr[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N:CL189 : cap1298_i2c.v(85) | Register bit data_wr[2] is always 0.
@N:CL189 : cap1298_i2c.v(85) | Register bit data_wr[3] is always 0.
@N:CL189 : cap1298_i2c.v(85) | Register bit data_wr[5] is always 0.
@N:CL189 : cap1298_i2c.v(85) | Register bit data_wr[7] is always 0.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit state_back[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit state_back[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : cap1298_i2c.v(85) | Pruning register bit 7 of data_wr[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : cap1298_i2c.v(85) | Pruning register bit 5 of data_wr[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : cap1298_i2c.v(85) | Pruning register bits 3 to 2 of data_wr[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : cap1298_i2c.v(85) | Pruning register bits 3 to 2 of state_back[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CG364 : display.v(18) | Synthesizing module display in library work.

@W:CG294 : display.v(28) | always block should contain at least one event control
@N:CG364 : cap1298_top.v(18) | Synthesizing module cap1298_top in library work.

@W:CG360 : cap1298_top.v(35) | Removing wire sensor_data2, as there is no assignment to it.
@W:CG360 : cap1298_top.v(36) | Removing wire sensor_data3, as there is no assignment to it.
@W:CG133 : cap1298_top.v(37) | Object touch_data is declared but not assigned. Either assign a value or remove the declaration.
@W:CL190 : cap1298_top.v(69) | Optimizing register bit key_num[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(69) | Optimizing register bit key_num[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(69) | Optimizing register bit key_num[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(69) | Optimizing register bit key_num[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(69) | Optimizing register bit key_num[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(69) | Optimizing register bit key_num[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(69) | Optimizing register bit key_num[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(69) | Optimizing register bit key_num[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(69) | Optimizing register bit key_num[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(69) | Optimizing register bit key_operate[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(69) | Optimizing register bit key_operate[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(69) | Optimizing register bit key_operate[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(184) | Optimizing register bit cnt[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : cap1298_top.v(184) | Pruning register bit 3 of cnt[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : cap1298_top.v(69) | Pruning register bits 8 to 7 of key_operate[8:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : cap1298_top.v(69) | Pruning register bit 0 of key_operate[8:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : cap1298_top.v(69) | Pruning register bit 10 of key_num[10:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : cap1298_top.v(69) | Pruning register bits 8 to 7 of key_num[10:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : cap1298_top.v(69) | Pruning register bits 5 to 0 of key_num[10:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CG364 : bin_bcd.v(8) | Synthesizing module bin_bcd in library work.

	B_SIZE=32'b00000000000000000000000000001100
   Generated name = bin_bcd_12s

@N:CG364 : compute.v(1) | Synthesizing module compute in library work.

@N:CG179 : compute.v(73) | Removing redundant assignment.
@N:CG179 : compute.v(74) | Removing redundant assignment.
@N:CG179 : compute.v(75) | Removing redundant assignment.
@N:CG179 : compute.v(76) | Removing redundant assignment.
@N:CG179 : compute.v(77) | Removing redundant assignment.
@N:CG179 : compute.v(78) | Removing redundant assignment.
@N:CG179 : compute.v(79) | Removing redundant assignment.
@N:CG179 : compute.v(80) | Removing redundant assignment.
@N:CG179 : compute.v(81) | Removing redundant assignment.
@N:CG179 : compute.v(82) | Removing redundant assignment.
@N:CG179 : compute.v(83) | Removing redundant assignment.
@W:CS263 : compute.v(215) | Port-width mismatch for port binary. Formal has width 12, Actual 16
@W:CG133 : compute.v(33) | Object cal_data_reg is declared but not assigned. Either assign a value or remove the declaration.
@W:CL169 : compute.v(35) | Pruning unused register cal_num_count[2:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : compute.v(35) | Pruning unused register value_result[15:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : compute.v(35) | Pruning unused register equal_flag. Make sure that there are no unused intermediate registers.
@W:CL271 : compute.v(35) | Pruning unused bits 15 to 12 of cal_result[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CL134 : compute.v(35) | Found RAM bcd_data_reg, depth=5, width=8
@A:CL282 : compute.v(229) | Feedback mux created for signal uart_data[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A:CL282 : compute.v(229) | Feedback mux created for signal cnt_delay[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A:CL282 : compute.v(35) | Feedback mux created for signal bcd_out_data[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@W:CL190 : compute.v(35) | Optimizing register bit cal_mode[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : compute.v(229) | Optimizing register bit data_out_reg[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : compute.v(229) | Pruning register bit 7 of data_out_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : compute.v(35) | Pruning register bit 3 of cal_mode[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CG364 : Baud.v(18) | Synthesizing module Baud in library work.

	BPS_PARA=32'b00000000000000000000000001101000
   Generated name = Baud_104s

@N:CG364 : Uart_Tx.v(18) | Synthesizing module Uart_Tx in library work.

@W:CL169 : Uart_Tx.v(36) | Pruning unused register rx_bps_en_r. Make sure that there are no unused intermediate registers.
@W:CL190 : Uart_Tx.v(50) | Optimizing register bit tx_data_r[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : Uart_Tx.v(50) | Pruning register bit 0 of tx_data_r[9:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CG364 : calculator.v(1) | Synthesizing module calculator in library work.

@W:CG360 : calculator.v(22) | Removing wire clk_pll, as there is no assignment to it.
@W:CG360 : calculator.v(24) | Removing wire sensor_data1, as there is no assignment to it.
@W:CG360 : calculator.v(25) | Removing wire sensor_data2, as there is no assignment to it.
@W:CG360 : calculator.v(26) | Removing wire sensor_data3, as there is no assignment to it.
@W:CG360 : calculator.v(41) | Removing wire lcd_gpioPIO_OUT, as there is no assignment to it.
@W:CG360 : calculator.v(42) | Removing wire lcd_sdaPIO_OUT, as there is no assignment to it.
@W:CG360 : calculator.v(42) | Removing wire lcd_sckPIO_OUT, as there is no assignment to it.
@W:CL156 : calculator.v(41) | *Input lcd_gpioPIO_OUT[1] to expression [buf] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W:CL156 : calculator.v(41) | *Input lcd_gpioPIO_OUT[0] to expression [buf] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W:CL156 : calculator.v(41) | *Input lcd_gpioPIO_OUT[2] to expression [buf] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W:CL157 : calculator.v(13) | *Output lcd_rst_out has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W:CL157 : calculator.v(14) | *Output lcd_cs_out has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W:CL157 : calculator.v(15) | *Output lcd_dc_out has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W:CL157 : calculator.v(16) | *Output lcd_clk_out has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W:CL157 : calculator.v(17) | *Output lcd_data_out has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@N:CL159 : calculator.v(7) | Input uart_in is unused.
@N:CL159 : Uart_Tx.v(27) | Input rx_bps_en is unused.
@W:CL190 : Baud.v(31) | Optimizing register bit cnt[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : Baud.v(31) | Optimizing register bit cnt[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : Baud.v(31) | Optimizing register bit cnt[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : Baud.v(31) | Optimizing register bit cnt[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : Baud.v(31) | Optimizing register bit cnt[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : Baud.v(31) | Optimizing register bit cnt[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : Baud.v(31) | Pruning register bits 12 to 7 of cnt[12:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL190 : compute.v(35) | Optimizing register bit operate_reg[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : compute.v(229) | Optimizing register bit cnt_send[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : compute.v(35) | Optimizing register bit cnt_convert[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:CL189 : compute.v(229) | Register bit cnt_delay[11] is always 0.
@N:CL189 : compute.v(229) | Register bit cnt_delay[12] is always 0.
@N:CL189 : compute.v(229) | Register bit cnt_delay[13] is always 0.
@N:CL189 : compute.v(229) | Register bit cnt_delay[14] is always 0.
@N:CL189 : compute.v(229) | Register bit cnt_delay[15] is always 0.
@N:CL189 : compute.v(229) | Register bit uart_data[7] is always 0.
@W:CL260 : compute.v(229) | Pruning register bit 7 of uart_data[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : compute.v(229) | Pruning register bits 15 to 11 of cnt_delay[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : compute.v(35) | Pruning register bit 3 of cnt_convert[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : compute.v(229) | Pruning register bit 3 of cnt_send[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : compute.v(35) | Pruning register bit 3 of operate_reg[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CL201 : compute.v(229) | Trying to extract state machine for register txstate.
Extracted state machine for register txstate
State machine has 6 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
@N:CL201 : compute.v(35) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 10 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
@W:CL279 : cap1298_top.v(131) | Pruning register bits 8 to 7 of operate_status[8:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : cap1298_top.v(116) | Pruning register bit 10 of num_status[10:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : cap1298_top.v(116) | Pruning register bits 8 to 7 of num_status[10:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : cap1298_top.v(116) | Pruning register bits 5 to 1 of num_status[10:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL190 : cap1298_top.v(116) | Optimizing register bit num_status[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(116) | Optimizing register bit num_status_r[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(116) | Optimizing register bit num_status_r[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(116) | Optimizing register bit num_status_r[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(116) | Optimizing register bit num_status_r[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(116) | Optimizing register bit num_status_r[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(116) | Optimizing register bit num_status_r[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(116) | Optimizing register bit num_status_r[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(116) | Optimizing register bit num_status_r[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(116) | Optimizing register bit num_status_r[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(131) | Optimizing register bit operate_status[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : cap1298_top.v(116) | Pruning register bit 10 of num_status_r[10:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : cap1298_top.v(116) | Pruning register bits 8 to 7 of num_status_r[10:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : cap1298_top.v(116) | Pruning register bits 5 to 0 of num_status_r[10:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : cap1298_top.v(131) | Pruning register bit 0 of operate_status[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL169 : cap1298_top.v(116) | Pruning unused register num_status[0]. Make sure that there are no unused intermediate registers.
@W:CL190 : cap1298_top.v(184) | Optimizing register bit cnt[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(184) | Optimizing register bit cnt[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_top.v(184) | Optimizing register bit cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : cap1298_top.v(131) | Pruning register bits 8 to 7 of operate_status_r[8:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : cap1298_top.v(131) | Pruning register bit 0 of operate_status_r[8:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL169 : cap1298_top.v(184) | Pruning unused register cnt[2:0]. Make sure that there are no unused intermediate registers.
@W:CL279 : cap1298_top.v(184) | Pruning register bits 7 to 6 of cnt[7:4]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL156 : cap1298_top.v(35) | *Input sensor_data2[7:0] to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W:CL156 : cap1298_top.v(36) | *Input sensor_data3[7:0] to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W:CL157 : cap1298_top.v(21) | *Output scl_out has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@N:CL159 : display.v(20) | Input rst_n_in is unused.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_idle[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_idle[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_idle[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_idle[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_idle[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_read[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_read[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_read[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_work[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_init[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_init[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_init[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : cap1298_i2c.v(85) | Optimizing register bit cnt_init[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : cap1298_i2c.v(85) | Pruning register bits 7 to 4 of cnt_init[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : cap1298_i2c.v(85) | Pruning register bit 4 of cnt_work[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : cap1298_i2c.v(85) | Pruning register bits 4 to 2 of cnt_read[4:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : cap1298_i2c.v(85) | Pruning register bits 7 to 3 of cnt_idle[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CL201 : cap1298_i2c.v(85) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 10 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
@W:CL249 : cap1298_i2c.v(85) | Initial value is not supported on state machine state

At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 77MB peak: 87MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Oct 26 14:30:52 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
File C:\Users\TEST\Desktop\calculator_fpga_mico8\impl1\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Oct 26 14:30:52 2017

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Oct 26 14:30:52 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
File C:\Users\TEST\Desktop\calculator_fpga_mico8\impl1\synwork\calculator_impl1_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Oct 26 14:30:53 2017

###########################################################]
Pre-mapping Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:MF827 :  | No constraint file specified. 
Linked File: calculator_impl1_scck.rpt
Printing clock  summary report in "C:\Users\TEST\Desktop\calculator_fpga_mico8\impl1\calculator_impl1_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
@W:BN132 : cap1298_i2c.v(85) | Removing sequential instance cap1298_top_u.cap1298_i2c_u1.data_wr[6] because it is equivalent to instance cap1298_top_u.cap1298_i2c_u1.data_wr[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=10  set on top level netlist calculator

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)



Clock Summary
*****************

Start                                    Requested     Requested     Clock                                Clock                   Clock
Clock                                    Frequency     Period        Type                                 Group                   Load 
---------------------------------------------------------------------------------------------------------------------------------------
calculator|clk_in                        1.0 MHz       1000.000      inferred                             Inferred_clkgroup_0     183  
cap1298_i2c|clk_200khz_derived_clock     1.0 MHz       1000.000      derived (from calculator|clk_in)     Inferred_clkgroup_0     66   
=======================================================================================================================================

@W:MT529 : compute.v(229) | Found inferred clock calculator|clk_in which controls 183 sequential elements including compute_u.data_out_reg[0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 142MB)

Encoding state machine txstate[5:0] (in view: work.compute(verilog))
original code -> new code
   000 -> 000001
   001 -> 000010
   010 -> 000100
   011 -> 001000
   100 -> 010000
   101 -> 100000
Encoding state machine state[9:0] (in view: work.compute(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
Encoding state machine state[9:0] (in view: work.cap1298_i2c(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 142MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 57MB peak: 142MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Oct 26 14:30:55 2017

###########################################################]
Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)

@N:MO111 : cap1298_top.v(43) | Tristate driver scl_out_1 (in view: work.cap1298_top(verilog)) on net scl_out_1 (in view: work.cap1298_top(verilog)) has its enable tied to GND.
@N:MO111 : cap1298_top.v(43) | Tristate driver scl_out_2 (in view: work.cap1298_top(verilog)) on net scl_out_2 (in view: work.cap1298_top(verilog)) has its enable tied to GND.
@N:MO111 : calculator.v(42) | Tristate driver lcd_data_out (in view: work.calculator(verilog)) on net lcd_data_out (in view: work.calculator(verilog)) has its enable tied to GND.
@N:MO111 : calculator.v(42) | Tristate driver lcd_clk_out (in view: work.calculator(verilog)) on net lcd_clk_out (in view: work.calculator(verilog)) has its enable tied to GND.
@N:MO111 : calculator.v(15) | Tristate driver lcd_dc_out (in view: work.calculator(verilog)) on net lcd_dc_out (in view: work.calculator(verilog)) has its enable tied to GND.
@N:MO111 : calculator.v(14) | Tristate driver lcd_cs_out (in view: work.calculator(verilog)) on net lcd_cs_out (in view: work.calculator(verilog)) has its enable tied to GND.
@N:MO111 : calculator.v(13) | Tristate driver lcd_rst_out (in view: work.calculator(verilog)) on net lcd_rst_out (in view: work.calculator(verilog)) has its enable tied to GND.
@N:MO111 :  | Tristate driver scl_out_t[1] (in view: work.calculator(verilog)) on net scl_out[1] (in view: work.calculator(verilog)) has its enable tied to GND. 
@N:MO111 :  | Tristate driver scl_out_t[2] (in view: work.calculator(verilog)) on net scl_out[2] (in view: work.calculator(verilog)) has its enable tied to GND. 

Available hyper_sources - for debug and ip models
	None Found

@N:MF236 : compute.v(136) | Generating a type div divider 
@N:FX493 :  | Applying initial value "0000000" on instance compute_u.data_out_reg[6:0]  
@N:FX493 :  | Applying initial value "000" on instance compute_u.operate_reg[2:0]  
@N:FX493 :  | Applying initial value "00000000" on instance cap1298_top_u.cap1298_i2c_u1.keys_status[7:0]  
@N:FX493 :  | Applying initial value "00" on instance cap1298_top_u.cap1298_i2c_u1.state_back[1:0]  
@N:FX493 :  | Applying initial value "000000" on instance cap1298_top_u.operate_status[6:1]  

Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 142MB)

Encoding state machine txstate[5:0] (in view: work.compute(verilog))
original code -> new code
   000 -> 000001
   001 -> 000010
   010 -> 000100
   011 -> 001000
   100 -> 010000
   101 -> 100000
Encoding state machine state[9:0] (in view: work.compute(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
@W:MO129 : compute.v(35) | Sequential instance compute_u.state[4] is reduced to a combinational gate by constant propagation.
@W:BN132 : compute.v(35) | Removing instance compute_u.cal_number[3] because it is equivalent to instance compute_u.cal_number[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : compute.v(35) | Removing instance compute_u.cal_number[2] because it is equivalent to instance compute_u.cal_number[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:MO160 : compute.v(229) | Register bit uart_data_1[6] (in view view:work.compute(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@N: : baud.v(31) | Found counter in view:work.Baud_104s(verilog) inst cnt[6:0]
@N: : uart_tx.v(66) | Found counter in view:work.Uart_Tx(verilog) inst num[3:0]
@N:BN362 : uart_tx.v(50) | Removing sequential instance tx_data_r[8] (in view: work.Uart_Tx(verilog)) because it does not drive other instances.
Encoding state machine state[9:0] (in view: work.cap1298_i2c(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
@N: : cap1298_i2c.v(85) | Found counter in view:work.cap1298_i2c(verilog) inst cnt_init[3:0]
@N: : cap1298_i2c.v(85) | Found counter in view:work.cap1298_i2c(verilog) inst cnt_work[3:0]

Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 148MB)

@N:BN362 : uart_tx.v(50) | Removing sequential instance Uart_Tx_u.tx_data_r[7] (in view: work.calculator(verilog)) because it does not drive other instances.

Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 159MB peak: 160MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 160MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 152MB peak: 160MB)

@N:FA113 : compute.v(53) | Pipelining module un1_value1[11:0]. For more information, search for "pipelining" in Online Help.
@N:MF169 : compute.v(35) | Pushed in register value1[15:0].
@N:MF169 : compute.v(35) | Pushed in register value2[15:0].
@N:MF169 : compute.v(35) | Pushed in register cal_number[3:0].

Starting Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 153MB peak: 160MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 153MB peak: 160MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 152MB peak: 160MB)


Finished preparing to map (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 160MB)


Finished technology mapping (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 202MB peak: 204MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:13s		   912.70ns		 798 /       254

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 202MB peak: 204MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
@N:MO111 : calculator.v(5) | Tristate driver scl_out_obuft_1_.un1[0] (in view: work.calculator(verilog)) on net scl_out[1] (in view: work.calculator(verilog)) has its enable tied to GND.
@N:FO126 : compute.v(35) | Generating RAM compute_u.bcd_data_reg[3:0]

Finished restoring hierarchy (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 201MB peak: 204MB)

@N:MT611 :  | Automatically generated clock cap1298_i2c|clk_200khz_derived_clock is not used and is being removed 


@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 255 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
66 instances converted, 0 sequential instances remain driven by gated/generated clocks

================================= Non-Gated/Non-Generated Clocks =================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance           
--------------------------------------------------------------------------------------------------
ClockId0001        clk_in              port                   255        compute_u.bcd_out_data[15]
==================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 165MB peak: 204MB)

Writing Analyst data base C:\Users\TEST\Desktop\calculator_fpga_mico8\impl1\synwork\calculator_impl1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:15s; Memory used current: 200MB peak: 204MB)

Writing EDIF Netlist and constraint files
@N:FX1056 :  | Writing EDF file: C:\Users\TEST\Desktop\calculator_fpga_mico8\impl1\calculator_impl1.edi 
L-2016.03L-1
@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:16s; Memory used current: 204MB peak: 206MB)


Start final timing analysis (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 202MB peak: 206MB)

@W:MT420 :  | Found inferred clock calculator|clk_in with period 1000.00ns. Please declare a user-defined clock on object "p:clk_in" 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Oct 26 14:31:13 2017
#


Top view:               calculator
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 



Performance Summary
*******************


Worst slack in design: 911.725

                      Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock        Frequency     Frequency     Period        Period        Slack       Type         Group              
--------------------------------------------------------------------------------------------------------------------------
calculator|clk_in     1.0 MHz       11.3 MHz      1000.000      88.275        911.725     inferred     Inferred_clkgroup_0
==========================================================================================================================





Clock Relationships
*******************

Clocks                                |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------
Starting           Ending             |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------
calculator|clk_in  calculator|clk_in  |  1000.000    911.725  |  No paths    -      |  No paths    -      |  No paths    -    
==============================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: calculator|clk_in
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                                            Arrival            
Instance                                 Reference             Type        Pin     Net                       Time        Slack  
                                         Clock                                                                                  
--------------------------------------------------------------------------------------------------------------------------------
compute_u.value2[0]                      calculator|clk_in     FD1P3DX     Q       value2[0]                 1.361       911.725
compute_u.value2[1]                      calculator|clk_in     FD1P3DX     Q       value2[1]                 1.321       911.908
compute_u.value2[2]                      calculator|clk_in     FD1P3DX     Q       value2[2]                 1.321       911.908
compute_u.cal_result_5.value2_pipe_1     calculator|clk_in     FD1P3DX     Q       mult1_un2_temp_b_1[1]     1.268       911.962
compute_u.value1[15]                     calculator|clk_in     FD1P3DX     Q       value1[15]                1.044       912.043
compute_u.value2[3]                      calculator|clk_in     FD1P3DX     Q       value2[3]                 1.319       912.053
compute_u.value2[4]                      calculator|clk_in     FD1P3DX     Q       value2[4]                 1.314       912.058
compute_u.cal_result_5.value2_pipe_2     calculator|clk_in     FD1P3DX     Q       mult1_un2_temp_b_1[2]     1.268       912.105
compute_u.cal_result_5.value2_pipe_3     calculator|clk_in     FD1P3DX     Q       mult1_un2_temp_b_1[3]     1.268       912.105
compute_u.value2[5]                      calculator|clk_in     FD1P3DX     Q       value2[5]                 1.314       912.201
================================================================================================================================


Ending Points with Worst Slack
******************************

                            Starting                                                      Required            
Instance                    Reference             Type        Pin     Net                 Time         Slack  
                            Clock                                                                             
--------------------------------------------------------------------------------------------------------------
compute_u.cal_result[0]     calculator|clk_in     FD1P3DX     D       cal_result_8[0]     1000.089     911.725
compute_u.cal_result[1]     calculator|clk_in     FD1P3DX     D       cal_result_8[1]     1000.089     916.835
compute_u.cal_result[2]     calculator|clk_in     FD1P3DX     D       cal_result_8[2]     1000.089     922.245
compute_u.cal_result[3]     calculator|clk_in     FD1P3DX     D       cal_result_8[3]     1000.089     927.655
compute_u.cal_result[4]     calculator|clk_in     FD1P3DX     D       cal_result_8[4]     1000.089     933.065
compute_u.cal_result[5]     calculator|clk_in     FD1P3DX     D       cal_result_8[5]     1000.089     938.475
compute_u.cal_result[6]     calculator|clk_in     FD1P3DX     D       cal_result_8[6]     1000.089     943.885
compute_u.cal_result[7]     calculator|clk_in     FD1P3DX     D       cal_result_8[7]     1000.089     949.295
compute_u.cal_result[8]     calculator|clk_in     FD1P3DX     D       cal_result_8[8]     1000.089     954.705
compute_u.cal_result[9]     calculator|clk_in     FD1P3DX     D       cal_result_8[9]     1000.089     961.131
==============================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.089

    - Propagation time:                      88.363
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     911.725

    Number of logic level(s):                162
    Starting point:                          compute_u.value2[0] / Q
    Ending point:                            compute_u.cal_result[0] / D
    The start point is clocked by            calculator|clk_in [rising] on pin CK
    The end   point is clocked by            calculator|clk_in [rising] on pin CK

Instance / Net                                                                            Pin      Pin               Arrival     No. of    
Name                                                                         Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------
compute_u.value2[0]                                                          FD1P3DX      Q        Out     1.361     1.361       -         
value2[0]                                                                    Net          -        -       -         -           55        
compute_u.cal_result_5.if_generate_plus\.mult1_un11_sum_cry_0_0              CCU2D        B1       In      0.000     1.361       -         
compute_u.cal_result_5.if_generate_plus\.mult1_un11_sum_cry_0_0              CCU2D        COUT     Out     1.545     2.906       -         
mult1_un11_sum_cry_0                                                         Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un11_sum_cry_1_0              CCU2D        CIN      In      0.000     2.906       -         
compute_u.cal_result_5.if_generate_plus\.mult1_un11_sum_cry_1_0              CCU2D        COUT     Out     0.143     3.049       -         
mult1_un11_sum_cry_2                                                         Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un11_sum_cry_3_0              CCU2D        CIN      In      0.000     3.049       -         
compute_u.cal_result_5.if_generate_plus\.mult1_un11_sum_cry_3_0              CCU2D        COUT     Out     0.143     3.192       -         
mult1_un11_sum_cry_4                                                         Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un11_sum_cry_5_0              CCU2D        CIN      In      0.000     3.192       -         
compute_u.cal_result_5.if_generate_plus\.mult1_un11_sum_cry_5_0              CCU2D        COUT     Out     0.143     3.334       -         
mult1_un11_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un11_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un11_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un11_sum_cry_12                                                        Net          -        -       -         -           1         
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mult1_un11_sum_cry_14                                                        Net          -        -       -         -           1         
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mult1_un11_sum_cry_16                                                        Net          -        -       -         -           1         
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mult1_un11_sum[17]                                                           Net          -        -       -         -           17        
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N_849                                                                        Net          -        -       -         -           1         
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mult1_un18_sum_cry_2                                                         Net          -        -       -         -           1         
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mult1_un18_sum_cry_4                                                         Net          -        -       -         -           1         
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mult1_un18_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un18_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un18_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un18_sum_cry_12                                                        Net          -        -       -         -           1         
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mult1_un18_sum_cry_14                                                        Net          -        -       -         -           1         
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mult1_un18_sum_cry_16                                                        Net          -        -       -         -           1         
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mult1_un18_sum[17]                                                           Net          -        -       -         -           17        
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N_851                                                                        Net          -        -       -         -           1         
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mult1_un25_sum_cry_2                                                         Net          -        -       -         -           1         
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mult1_un25_sum_cry_4                                                         Net          -        -       -         -           1         
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mult1_un25_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un25_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un25_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un25_sum_cry_12                                                        Net          -        -       -         -           1         
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mult1_un25_sum_cry_14                                                        Net          -        -       -         -           1         
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mult1_un25_sum_cry_16                                                        Net          -        -       -         -           1         
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mult1_un25_sum[17]                                                           Net          -        -       -         -           17        
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N_853                                                                        Net          -        -       -         -           1         
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mult1_un32_sum_cry_2                                                         Net          -        -       -         -           1         
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mult1_un32_sum_cry_4                                                         Net          -        -       -         -           1         
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mult1_un32_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un32_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un32_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un32_sum_cry_12                                                        Net          -        -       -         -           1         
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mult1_un32_sum_cry_14                                                        Net          -        -       -         -           1         
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mult1_un32_sum_cry_16                                                        Net          -        -       -         -           1         
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mult1_un32_sum[17]                                                           Net          -        -       -         -           17        
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N_855                                                                        Net          -        -       -         -           1         
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mult1_un39_sum_cry_2                                                         Net          -        -       -         -           1         
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mult1_un39_sum_cry_4                                                         Net          -        -       -         -           1         
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mult1_un39_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un39_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un39_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un39_sum_cry_12                                                        Net          -        -       -         -           1         
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mult1_un39_sum_cry_14                                                        Net          -        -       -         -           1         
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mult1_un39_sum_cry_16                                                        Net          -        -       -         -           1         
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mult1_un39_sum[17]                                                           Net          -        -       -         -           18        
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N_857                                                                        Net          -        -       -         -           1         
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mult1_un46_sum_cry_2                                                         Net          -        -       -         -           1         
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mult1_un46_sum_cry_4                                                         Net          -        -       -         -           1         
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mult1_un46_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un46_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un46_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un46_sum_cry_12                                                        Net          -        -       -         -           1         
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mult1_un46_sum_cry_14                                                        Net          -        -       -         -           1         
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mult1_un46_sum_cry_16                                                        Net          -        -       -         -           1         
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mult1_un46_sum[17]                                                           Net          -        -       -         -           18        
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N_858                                                                        Net          -        -       -         -           1         
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mult1_un53_sum_cry_2                                                         Net          -        -       -         -           1         
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mult1_un53_sum_cry_4                                                         Net          -        -       -         -           1         
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mult1_un53_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un53_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un53_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un53_sum_cry_12                                                        Net          -        -       -         -           1         
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mult1_un53_sum_cry_14                                                        Net          -        -       -         -           1         
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mult1_un53_sum_cry_16                                                        Net          -        -       -         -           1         
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mult1_un53_sum[17]                                                           Net          -        -       -         -           18        
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N_859                                                                        Net          -        -       -         -           1         
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mult1_un60_sum_cry_2                                                         Net          -        -       -         -           1         
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mult1_un60_sum_cry_4                                                         Net          -        -       -         -           1         
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mult1_un60_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un60_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un60_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un60_sum_cry_12                                                        Net          -        -       -         -           1         
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mult1_un60_sum_cry_14                                                        Net          -        -       -         -           1         
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mult1_un60_sum_cry_16                                                        Net          -        -       -         -           1         
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mult1_un60_sum[17]                                                           Net          -        -       -         -           18        
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N_860                                                                        Net          -        -       -         -           1         
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mult1_un67_sum_cry_2                                                         Net          -        -       -         -           1         
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mult1_un67_sum_cry_4                                                         Net          -        -       -         -           1         
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mult1_un67_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un67_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un67_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un67_sum_cry_12                                                        Net          -        -       -         -           1         
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mult1_un67_sum_cry_14                                                        Net          -        -       -         -           1         
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mult1_un67_sum_cry_16                                                        Net          -        -       -         -           1         
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mult1_un67_sum[17]                                                           Net          -        -       -         -           18        
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N_861                                                                        Net          -        -       -         -           1         
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mult1_un74_sum_cry_2                                                         Net          -        -       -         -           1         
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mult1_un74_sum_cry_4                                                         Net          -        -       -         -           1         
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mult1_un74_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un74_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un74_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un74_sum_cry_12                                                        Net          -        -       -         -           1         
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mult1_un74_sum_cry_14                                                        Net          -        -       -         -           1         
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mult1_un74_sum_cry_16                                                        Net          -        -       -         -           1         
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mult1_un74_sum[17]                                                           Net          -        -       -         -           18        
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N_837                                                                        Net          -        -       -         -           1         
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mult1_un81_sum_cry_2                                                         Net          -        -       -         -           1         
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mult1_un81_sum_cry_4                                                         Net          -        -       -         -           1         
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mult1_un81_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un81_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un81_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un81_sum_cry_12                                                        Net          -        -       -         -           1         
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mult1_un81_sum_cry_14                                                        Net          -        -       -         -           1         
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mult1_un81_sum_cry_16                                                        Net          -        -       -         -           1         
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mult1_un81_sum[17]                                                           Net          -        -       -         -           18        
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N_839                                                                        Net          -        -       -         -           1         
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mult1_un88_sum_cry_2                                                         Net          -        -       -         -           1         
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mult1_un88_sum_cry_4                                                         Net          -        -       -         -           1         
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mult1_un88_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un88_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un88_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un88_sum_cry_12                                                        Net          -        -       -         -           1         
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mult1_un88_sum_cry_14                                                        Net          -        -       -         -           1         
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mult1_un88_sum_cry_16                                                        Net          -        -       -         -           1         
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mult1_un88_sum[17]                                                           Net          -        -       -         -           18        
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N_841                                                                        Net          -        -       -         -           1         
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mult1_un95_sum_cry_2                                                         Net          -        -       -         -           1         
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mult1_un95_sum_cry_4                                                         Net          -        -       -         -           1         
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mult1_un95_sum_cry_6                                                         Net          -        -       -         -           1         
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mult1_un95_sum_cry_8                                                         Net          -        -       -         -           1         
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mult1_un95_sum_cry_10                                                        Net          -        -       -         -           1         
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mult1_un95_sum_cry_12                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un95_sum_cry_13_0             CCU2D        CIN      In      0.000     68.665      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un95_sum_cry_13_0             CCU2D        COUT     Out     0.143     68.808      -         
mult1_un95_sum_cry_14                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un95_sum_cry_15_0             CCU2D        CIN      In      0.000     68.808      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un95_sum_cry_15_0             CCU2D        COUT     Out     0.143     68.951      -         
mult1_un95_sum_cry_16                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un95_sum_s_17_0               CCU2D        CIN      In      0.000     68.951      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un95_sum_s_17_0               CCU2D        S0       Out     1.849     70.800      -         
mult1_un95_sum[17]                                                           Net          -        -       -         -           18        
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_1_0_RNO         ORCALUT4     B        In      0.000     70.800      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_1_0_RNO         ORCALUT4     Z        Out     1.017     71.817      -         
N_843                                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_1_0             CCU2D        C0       In      0.000     71.817      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_1_0             CCU2D        COUT     Out     1.545     73.361      -         
mult1_un102_sum_cry_2                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_3_0             CCU2D        CIN      In      0.000     73.361      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_3_0             CCU2D        COUT     Out     0.143     73.504      -         
mult1_un102_sum_cry_4                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_5_0             CCU2D        CIN      In      0.000     73.504      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_5_0             CCU2D        COUT     Out     0.143     73.647      -         
mult1_un102_sum_cry_6                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_7_0             CCU2D        CIN      In      0.000     73.647      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_7_0             CCU2D        COUT     Out     0.143     73.790      -         
mult1_un102_sum_cry_8                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_9_0             CCU2D        CIN      In      0.000     73.790      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_9_0             CCU2D        COUT     Out     0.143     73.933      -         
mult1_un102_sum_cry_10                                                       Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_11_0            CCU2D        CIN      In      0.000     73.933      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_11_0            CCU2D        COUT     Out     0.143     74.075      -         
mult1_un102_sum_cry_12                                                       Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_13_0            CCU2D        CIN      In      0.000     74.075      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_13_0            CCU2D        COUT     Out     0.143     74.218      -         
mult1_un102_sum_cry_14                                                       Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_15_0            CCU2D        CIN      In      0.000     74.218      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_cry_15_0            CCU2D        COUT     Out     0.143     74.361      -         
mult1_un102_sum_cry_16                                                       Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_s_17_0              CCU2D        CIN      In      0.000     74.361      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un102_sum_s_17_0              CCU2D        S0       Out     1.849     76.210      -         
mult1_un102_sum[17]                                                          Net          -        -       -         -           18        
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_1_0_RNO         ORCALUT4     B        In      0.000     76.210      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_1_0_RNO         ORCALUT4     Z        Out     1.017     77.227      -         
N_845                                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_1_0             CCU2D        C0       In      0.000     77.227      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_1_0             CCU2D        COUT     Out     1.545     78.771      -         
mult1_un109_sum_cry_2                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_3_0             CCU2D        CIN      In      0.000     78.771      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_3_0             CCU2D        COUT     Out     0.143     78.914      -         
mult1_un109_sum_cry_4                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_5_0             CCU2D        CIN      In      0.000     78.914      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_5_0             CCU2D        COUT     Out     0.143     79.057      -         
mult1_un109_sum_cry_6                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_7_0             CCU2D        CIN      In      0.000     79.057      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_7_0             CCU2D        COUT     Out     0.143     79.200      -         
mult1_un109_sum_cry_8                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_9_0             CCU2D        CIN      In      0.000     79.200      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_9_0             CCU2D        COUT     Out     0.143     79.343      -         
mult1_un109_sum_cry_10                                                       Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_11_0            CCU2D        CIN      In      0.000     79.343      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_11_0            CCU2D        COUT     Out     0.143     79.485      -         
mult1_un109_sum_cry_12                                                       Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_13_0            CCU2D        CIN      In      0.000     79.485      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_13_0            CCU2D        COUT     Out     0.143     79.628      -         
mult1_un109_sum_cry_14                                                       Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_15_0            CCU2D        CIN      In      0.000     79.628      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_cry_15_0            CCU2D        COUT     Out     0.143     79.771      -         
mult1_un109_sum_cry_16                                                       Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_s_17_0              CCU2D        CIN      In      0.000     79.771      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un109_sum_s_17_0              CCU2D        S0       Out     1.849     81.620      -         
mult1_un109_sum[17]                                                          Net          -        -       -         -           18        
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_1_0_RNO         ORCALUT4     B        In      0.000     81.620      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_1_0_RNO         ORCALUT4     Z        Out     1.017     82.637      -         
N_847                                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_1_0             CCU2D        C0       In      0.000     82.637      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_1_0             CCU2D        COUT     Out     1.545     84.181      -         
mult1_un116_sum_cry_2                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_3_0             CCU2D        CIN      In      0.000     84.181      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_3_0             CCU2D        COUT     Out     0.143     84.324      -         
mult1_un116_sum_cry_4                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_5_0             CCU2D        CIN      In      0.000     84.324      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_5_0             CCU2D        COUT     Out     0.143     84.467      -         
mult1_un116_sum_cry_6                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_7_0             CCU2D        CIN      In      0.000     84.467      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_7_0             CCU2D        COUT     Out     0.143     84.610      -         
mult1_un116_sum_cry_8                                                        Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_9_0             CCU2D        CIN      In      0.000     84.610      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_9_0             CCU2D        COUT     Out     0.143     84.752      -         
mult1_un116_sum_cry_10                                                       Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_11_0            CCU2D        CIN      In      0.000     84.752      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_11_0            CCU2D        COUT     Out     0.143     84.895      -         
mult1_un116_sum_cry_12                                                       Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_13_0            CCU2D        CIN      In      0.000     84.895      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_13_0            CCU2D        COUT     Out     0.143     85.038      -         
mult1_un116_sum_cry_14                                                       Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_15_0            CCU2D        CIN      In      0.000     85.038      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_cry_15_0            CCU2D        COUT     Out     0.143     85.181      -         
mult1_un116_sum_cry_16                                                       Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_s_17_0              CCU2D        CIN      In      0.000     85.181      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_s_17_0              CCU2D        S0       Out     1.549     86.730      -         
mult1_un116_sum_s_17_0_S0                                                    Net          -        -       -         -           1         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_s_17_0_RNI4RM33     ORCALUT4     B        In      0.000     86.730      -         
compute_u.cal_result_5.if_generate_plus\.mult1_un116_sum_s_17_0_RNI4RM33     ORCALUT4     Z        Out     1.017     87.747      -         
N_6                                                                          Net          -        -       -         -           1         
compute_u.cal_result_8[0]                                                    ORCALUT4     B        In      0.000     87.747      -         
compute_u.cal_result_8[0]                                                    ORCALUT4     Z        Out     0.617     88.363      -         
cal_result_8[0]                                                              Net          -        -       -         -           1         
compute_u.cal_result[0]                                                      FD1P3DX      D        In      0.000     88.363      -         
===========================================================================================================================================



##### END OF TIMING REPORT #####]

Constraints that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 202MB peak: 206MB)


Finished timing report (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 202MB peak: 206MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2_4000hc-4

Register bits: 254 of 4320 (6%)
PIC Latch:       0
I/O cells:       39


Details:
BB:             1
CCU2D:          240
DPR16X4C:       1
FD1P3AX:        21
FD1P3BX:        9
FD1P3DX:        154
FD1P3IX:        4
FD1S3BX:        2
FD1S3DX:        51
FD1S3IX:        11
GSR:            1
IB:             2
INV:            13
OB:             29
OBZ:            7
OFS1P3BX:       2
ORCALUT4:       781
PFUMX:          1
PUR:            1
VHI:            6
VLO:            8
true:           2
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 34MB peak: 206MB)

Process took 0h:00m:17s realtime, 0h:00m:17s cputime
# Thu Oct 26 14:31:13 2017

###########################################################]