Setting log file to 'C:/Users/TEST/Desktop/calculator_fpga/calculator_lcd/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/calculator_fpga/calculator_lcd/calculator_lcd.v
INFO - C:/Users/TEST/Desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(9,8-9,22) (VERI-1018) compiling module calculator_lcd
INFO - C:/Users/TEST/Desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(9,1-312,10) (VERI-9000) elaborating module 'calculator_lcd'
Done: design load finished with (0) errors, and (0) warnings