Synthesis Report
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul  4 2016
#install: C:\lscc\diamond\3.8_x64\synpbase
#OS: Windows 7 6.1
#Hostname: TEST-PC

# Sat Sep 23 19:51:59 2017

#Implementation: impl1

Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Synopsys Verilog Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v" (library work)
Verilog syntax check successful!
File C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v changed - recompiling
Selecting top level module JLX12832G_lcd
@N: CG364 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":9:7:9:19|Synthesizing module JLX12832G_lcd in library work.

@W: CG532 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":108:0:108:6|Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":61:10:61:24|Object send_clear_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_0_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_1_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_2_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_3_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_4_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_5_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_6_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_7_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_8_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_9_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_10_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_11_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_12_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_13_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_14_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_15_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_16_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_17_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_18_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_19_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_20_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_21_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_22_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_23_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_24_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_25_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_26_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":106:11:106:13|Object mem_27_ is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Pruning unused register mem_num[7:0]. Make sure that there are no unused intermediate registers.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal temp[63:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal shift_flag -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal shift_cnt[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal lcd_dc_reg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal lcd_data_out_reg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal delay_cnt[25:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal data_reg[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal data_cnt[8:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal cnt_main[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal cnt_init[4:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal cnt_display[4:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal cnt_clear[4:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal cmd_reg[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Feedback mux created for signal byte_send_out[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":147:0:147:5|Feedback mux created for signal clk_div -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Register bit data_reg[0] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Register bit data_reg[1] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Register bit data_reg[2] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Register bit data_reg[3] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Register bit data_reg[4] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Register bit data_reg[5] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Register bit data_reg[6] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Register bit data_reg[7] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Register bit cnt_main[2] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Register bit cnt_main[3] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Register bit cnt_display[4] is always 0.
@W: CL260 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Pruning register bit 4 of cnt_display[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Pruning register bits 3 to 2 of cnt_main[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N: CL201 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Trying to extract state machine for register main_state.
Extracted state machine for register main_state
State machine has 16 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
   1101
   1110
   1111
@W: CL249 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":178:0:178:5|Initial value is not supported on state machine main_state
@N: CL201 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":158:0:158:5|Trying to extract state machine for register clk_div_state.
Extracted state machine for register clk_div_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W: CL249 :"C:\Users\TEST\Desktop\calculator_lcd\JLX12832G_lcd.v":158:0:158:5|Initial value is not supported on state machine clk_div_state

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Sep 23 19:52:00 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
@N|Running in 64-bit mode
File C:\Users\TEST\Desktop\calculator_lcd\impl1\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Sep 23 19:52:00 2017

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Sep 23 19:52:00 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
@N|Running in 64-bit mode
File C:\Users\TEST\Desktop\calculator_lcd\impl1\synwork\calculator_lcd_impl1_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Sep 23 19:52:01 2017

###########################################################]
Pre-mapping Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A: MF827 |No constraint file specified.
@L: C:\Users\TEST\Desktop\calculator_lcd\impl1\calculator_lcd_impl1_scck.rpt 
Printing clock  summary report in "C:\Users\TEST\Desktop\calculator_lcd\impl1\calculator_lcd_impl1_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@W: BN288 :"c:\users\test\desktop\calculator_lcd\jlx12832g_lcd.v":178:0:178:5|Register lcd_cs_reg with set has an initial value of 0. Ignoring initial value.  
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=10  set on top level netlist JLX12832G_lcd

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)



Clock Summary
*****************

Start                    Requested     Requested     Clock        Clock                   Clock
Clock                    Frequency     Period        Type         Group                   Load 
-----------------------------------------------------------------------------------------------
JLX12832G_lcd|clk_in     1.0 MHz       1000.000      inferred     Inferred_clkgroup_0     185  
===============================================================================================

@W: MT529 :"c:\users\test\desktop\calculator_lcd\jlx12832g_lcd.v":178:0:178:5|Found inferred clock JLX12832G_lcd|clk_in which controls 185 sequential elements including lcd_dc_reg. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

Encoding state machine main_state[15:0] (in view: work.JLX12832G_lcd(verilog))
original code -> new code
   0000 -> 0000000000000001
   0001 -> 0000000000000010
   0010 -> 0000000000000100
   0011 -> 0000000000001000
   0100 -> 0000000000010000
   0101 -> 0000000000100000
   0110 -> 0000000001000000
   0111 -> 0000000010000000
   1000 -> 0000000100000000
   1001 -> 0000001000000000
   1010 -> 0000010000000000
   1011 -> 0000100000000000
   1100 -> 0001000000000000
   1101 -> 0010000000000000
   1110 -> 0100000000000000
   1111 -> 1000000000000000
Encoding state machine clk_div_state[3:0] (in view: work.JLX12832G_lcd(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MO225 :"c:\users\test\desktop\calculator_lcd\jlx12832g_lcd.v":158:0:158:5|There are no possible illegal states for state machine clk_div_state[3:0] (in view: work.JLX12832G_lcd(verilog)); safe FSM implementation is not required.
None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 141MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Sep 23 19:52:02 2017

###########################################################]
Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Available hyper_sources - for debug and ip models
	None Found

@N: FX493 |Applying initial value "00000000" on instance cmd_reg[7:0] 
@N: FX493 |Applying initial value "0000" on instance main_state_back[3:0] 
@N: FX493 |Applying initial value "00000000" on instance byte_send_out[7:0] 
@N: FX493 |Applying initial value "0000000000000000000000000000000000000000000000000000000000000000" on instance temp[63:0] 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

Encoding state machine main_state[15:0] (in view: work.JLX12832G_lcd(verilog))
original code -> new code
   0000 -> 0000000000000001
   0001 -> 0000000000000010
   0010 -> 0000000000000100
   0011 -> 0000000000001000
   0100 -> 0000000000010000
   0101 -> 0000000000100000
   0110 -> 0000000001000000
   0111 -> 0000000010000000
   1000 -> 0000000100000000
   1001 -> 0000001000000000
   1010 -> 0000010000000000
   1011 -> 0000100000000000
   1100 -> 0001000000000000
   1101 -> 0010000000000000
   1110 -> 0100000000000000
   1111 -> 1000000000000000
Encoding state machine clk_div_state[3:0] (in view: work.JLX12832G_lcd(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MO225 :"c:\users\test\desktop\calculator_lcd\jlx12832g_lcd.v":158:0:158:5|There are no possible illegal states for state machine clk_div_state[3:0] (in view: work.JLX12832G_lcd(verilog)); safe FSM implementation is not required.

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 147MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 147MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 147MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 147MB)


Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 143MB peak: 147MB)


Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 171MB peak: 173MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:02s		   991.51ns		 295 /       183

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 171MB peak: 173MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 171MB peak: 173MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 119 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

============================ Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance 
----------------------------------------------------------------------------------------
@K:CKID0001       clk_in              port                   119        byte_send_out[0]
========================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 139MB peak: 173MB)

Writing Analyst data base C:\Users\TEST\Desktop\calculator_lcd\impl1\synwork\calculator_lcd_impl1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 172MB peak: 174MB)

Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Users\TEST\Desktop\calculator_lcd\impl1\calculator_lcd_impl1.edi
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 176MB peak: 178MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 175MB peak: 178MB)

@W: MT420 |Found inferred clock JLX12832G_lcd|clk_in with period 1000.00ns. Please declare a user-defined clock on object "p:clk_in"


##### START OF TIMING REPORT #####[
# Timing Report written on Sat Sep 23 19:52:07 2017
#


Top view:               JLX12832G_lcd
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary
*******************


Worst slack in design: 990.813

                         Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock           Frequency     Frequency     Period        Period        Slack       Type         Group              
-----------------------------------------------------------------------------------------------------------------------------
JLX12832G_lcd|clk_in     1.0 MHz       108.8 MHz     1000.000      9.187         990.813     inferred     Inferred_clkgroup_0
=============================================================================================================================





Clock Relationships
*******************

Clocks                                      |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------
Starting              Ending                |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------
JLX12832G_lcd|clk_in  JLX12832G_lcd|clk_in  |  1000.000    990.813  |  No paths    -      |  No paths    -      |  No paths    -    
====================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: JLX12832G_lcd|clk_in
====================================



Starting Points with Worst Slack
********************************

                  Starting                                                       Arrival            
Instance          Reference                Type        Pin     Net               Time        Slack  
                  Clock                                                                             
----------------------------------------------------------------------------------------------------
shift_cnt[0]      JLX12832G_lcd|clk_in     FD1S3AX     Q       shift_cnt[0]      1.044       990.813
shift_cnt[1]      JLX12832G_lcd|clk_in     FD1S3AX     Q       shift_cnt[1]      1.044       990.813
shift_cnt[3]      JLX12832G_lcd|clk_in     FD1S3AX     Q       shift_cnt[3]      1.044       990.813
shift_cnt[5]      JLX12832G_lcd|clk_in     FD1S3AX     Q       shift_cnt[5]      1.044       990.813
shift_cnt[6]      JLX12832G_lcd|clk_in     FD1S3AX     Q       shift_cnt[6]      1.044       990.813
shift_cnt[7]      JLX12832G_lcd|clk_in     FD1S3AX     Q       shift_cnt[7]      1.044       990.813
main_state[7]     JLX12832G_lcd|clk_in     FD1S3DX     Q       main_state[7]     1.284       991.693
shift_cnt[2]      JLX12832G_lcd|clk_in     FD1S3AX     Q       shift_cnt[2]      1.044       991.830
shift_cnt[4]      JLX12832G_lcd|clk_in     FD1S3AX     Q       shift_cnt[4]      1.044       991.830
shift_flag        JLX12832G_lcd|clk_in     FD1P3AX     Q       shift_flag        1.148       991.830
====================================================================================================


Ending Points with Worst Slack
******************************

                  Starting                                                            Required            
Instance          Reference                Type        Pin     Net                    Time         Slack  
                  Clock                                                                                   
----------------------------------------------------------------------------------------------------------
shift_cnt[3]      JLX12832G_lcd|clk_in     FD1S3AX     D       shift_cnt_8[3]         1000.089     990.813
shift_cnt[7]      JLX12832G_lcd|clk_in     FD1S3AX     D       un1_shift_cnt_7[7]     999.894      990.949
shift_cnt[5]      JLX12832G_lcd|clk_in     FD1S3AX     D       un1_shift_cnt_7[5]     999.894      991.092
shift_cnt[6]      JLX12832G_lcd|clk_in     FD1S3AX     D       un1_shift_cnt_7[6]     999.894      991.092
shift_cnt[4]      JLX12832G_lcd|clk_in     FD1S3AX     D       un1_shift_cnt_7[4]     999.894      991.235
shift_cnt[1]      JLX12832G_lcd|clk_in     FD1S3AX     D       un1_shift_cnt_7[1]     999.894      991.378
shift_cnt[2]      JLX12832G_lcd|clk_in     FD1S3AX     D       un1_shift_cnt_7[2]     999.894      991.378
main_state[2]     JLX12832G_lcd|clk_in     FD1S3DX     D       N_821_i                1000.089     991.671
main_state[3]     JLX12832G_lcd|clk_in     FD1S3DX     D       N_823_i                1000.089     991.671
main_state[4]     JLX12832G_lcd|clk_in     FD1S3DX     D       N_825_i                1000.089     991.735
==========================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.089

    - Propagation time:                      9.276
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     990.813

    Number of logic level(s):                8
    Starting point:                          shift_cnt[0] / Q
    Ending point:                            shift_cnt[3] / D
    The start point is clocked by            JLX12832G_lcd|clk_in [rising] on pin CK
    The end   point is clocked by            JLX12832G_lcd|clk_in [rising] on pin CK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                              Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
shift_cnt[0]                      FD1S3AX      Q        Out     1.044     1.044       -         
shift_cnt[0]                      Net          -        -       -         -           2         
shift_cnt4_4                      ORCALUT4     A        In      0.000     1.044       -         
shift_cnt4_4                      ORCALUT4     Z        Out     1.017     2.061       -         
shift_cnt4_4                      Net          -        -       -         -           1         
shift_cnt4                        ORCALUT4     B        In      0.000     2.061       -         
shift_cnt4                        ORCALUT4     Z        Out     1.193     3.253       -         
shift_cnt4                        Net          -        -       -         -           4         
lcd_data_out_reg_0_sqmuxa_2       ORCALUT4     D        In      0.000     3.253       -         
lcd_data_out_reg_0_sqmuxa_2       ORCALUT4     Z        Out     1.153     4.406       -         
lcd_data_out_reg_0_sqmuxa_2       Net          -        -       -         -           3         
un1_lcd_data_out_reg_0_sqmuxa     ORCALUT4     B        In      0.000     4.406       -         
un1_lcd_data_out_reg_0_sqmuxa     ORCALUT4     Z        Out     1.017     5.423       -         
un1_lcd_data_out_reg_0_sqmuxa     Net          -        -       -         -           1         
un1_shift_cnt_7_cry_0_0           CCU2D        B0       In      0.000     5.423       -         
un1_shift_cnt_7_cry_0_0           CCU2D        COUT     Out     1.545     6.968       -         
un1_shift_cnt_7_cry_0             Net          -        -       -         -           1         
un1_shift_cnt_7_cry_1_0           CCU2D        CIN      In      0.000     6.968       -         
un1_shift_cnt_7_cry_1_0           CCU2D        COUT     Out     0.143     7.110       -         
un1_shift_cnt_7_cry_2             Net          -        -       -         -           1         
un1_shift_cnt_7_cry_3_0           CCU2D        CIN      In      0.000     7.110       -         
un1_shift_cnt_7_cry_3_0           CCU2D        S0       Out     1.549     8.659       -         
un1_shift_cnt_7_cry_3_0_S0        Net          -        -       -         -           1         
shift_cnt_8[3]                    ORCALUT4     A        In      0.000     8.659       -         
shift_cnt_8[3]                    ORCALUT4     Z        Out     0.617     9.276       -         
shift_cnt_8[3]                    Net          -        -       -         -           1         
shift_cnt[3]                      FD1S3AX      D        In      0.000     9.276       -         
================================================================================================



##### END OF TIMING REPORT #####]

Constraints that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 175MB peak: 178MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 175MB peak: 178MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2_4000hc-4

Register bits: 119 of 4320 (3%)
PIC Latch:       0
I/O cells:       7


Details:
CCU2D:          33
FD1P3AX:        18
FD1P3AY:        1
FD1P3BX:        1
FD1P3DX:        5
FD1S3AX:        29
FD1S3BX:        1
FD1S3DX:        33
FD1S3IX:        30
GSR:            1
IB:             2
INV:            2
OB:             5
OFS1P3DX:       1
ORCALUT4:       222
PUR:            1
VHI:            1
VLO:            1
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 31MB peak: 178MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Sat Sep 23 19:52:07 2017

###########################################################]