Lattice Mapping Report File for Design Module 'cap1298_top' Design Information Command line: map -a MachXO2 -p LCMXO2-4000HC -t CSBGA132 -s 4 -oc Commercial cap1298_impl1.ngd -o cap1298_impl1_map.ncd -pr cap1298_impl1.prf -mp cap1298_impl1.mrp -lpf C:/Users/TEST/Desktop/calculator_fpga/calculator_cap 1298/impl1/cap1298_impl1_synplify.lpf -lpf C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/cap1298.lpf -c 0 -gui -msgset C:/Users/TEST/Desktop/calculator_fpga/calculator_cap1298/promote.xml Target Vendor: LATTICE Target Device: LCMXO2-4000HCCSBGA132 Target Performance: 4 Mapper: xo2c00, version: Diamond (64-bit) 3.8.0.115.3 Mapped on: 11/01/17 16:44:26 Design Summary Number of registers: 259 out of 4635 (6%) PFU registers: 256 out of 4320 (6%) PIO registers: 3 out of 315 (1%) Number of SLICEs: 312 out of 2160 (14%) SLICEs as Logic/ROM: 312 out of 2160 (14%) SLICEs as RAM: 0 out of 1620 (0%) SLICEs as Carry: 0 out of 2160 (0%) Number of LUT4s: 623 out of 4320 (14%) Number used as logic LUTs: 623 Number used as distributed RAM: 0 Number used as ripple logic: 0 Number used as shift registers: 0 Number of PIO sites used: 34 + 4(JTAG) out of 105 (36%) Number of block RAMs: 0 out of 10 (0%) Number of GSRs: 1 out of 1 (100%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%) Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Number of PLLs: 0 out of 2 (0%) Number of DQSDLLs: 0 out of 2 (0%) Number of CLKDIVC: 0 out of 4 (0%) Number of ECLKSYNCA: 0 out of 4 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 1 Net clk_in_c: 144 loads, 144 rising, 0 falling (Driver: PIO clk_in ) Number of Clock Enables: 30 Net un1_cnt25_i_0: 2 loads, 2 LSLICEs Net scl_out_r_0_sqmuxa_3_RNIDKQN1: 1 loads, 0 LSLICEs Net cap1298_i2c_u3/sda_out_r_RNO_1: 1 loads, 1 LSLICEs Net cap1298_i2c_u3/clk_200khz_RNIEJCI1: 2 loads, 2 LSLICEs Net cap1298_i2c_u3/clk_200khz_RNIFKCI1: 2 loads, 2 LSLICEs Net cap1298_i2c_u3/clk_200khz_RNI6TJO: 20 loads, 20 LSLICEs Net cap1298_i2c_u3/un31_0_m2_RNIVQKL1: 4 loads, 4 LSLICEs Net cap1298_i2c_u3/state_RNIK09V1[2]: 1 loads, 1 LSLICEs Net cap1298_i2c_u3/state_ns_0_a5_0_RNI4FD01[8]: 4 loads, 4 LSLICEs Net cap1298_i2c_u3/un1_cnt_200khz12_0_a3_RNIQDV86: 2 loads, 2 LSLICEs Net scl_out_r_0_sqmuxa_3_RNI52FF3: 1 loads, 0 LSLICEs Net cap1298_i2c_u2/clk_200khz_RNIA3131: 2 loads, 2 LSLICEs Net cap1298_i2c_u2/clk_200khz_RNIB4131: 2 loads, 2 LSLICEs Net cap1298_i2c_u2/sda_out_r_RNO_0: 1 loads, 1 LSLICEs Net cap1298_i2c_u2/clk_200khz_RNI4VGJ: 20 loads, 20 LSLICEs Net cap1298_i2c_u2/un31_0_m2_RNIQTT31: 4 loads, 4 LSLICEs Net cap1298_i2c_u2/state_RNIF7PA1[2]: 1 loads, 1 LSLICEs Net cap1298_i2c_u2/state_ns_0_a5_0_RNI1UUS[8]: 4 loads, 4 LSLICEs Net cap1298_i2c_u2/un1_cnt_200khz12_0_3_RNINGI43: 2 loads, 2 LSLICEs Net scl_out_r_0_sqmuxa_3_RNIL9TR1: 1 loads, 0 LSLICEs Net cap1298_i2c_u1/clk_200khz_RNI21EE: 20 loads, 20 LSLICEs Net cap1298_i2c_u1/un1_cnt_200khz12_0_a3_RNI7K712: 2 loads, 2 LSLICEs Net cap1298_i2c_u1/clk_200khz_RNI7KLJ: 2 loads, 2 LSLICEs Net cap1298_i2c_u1/sda_out_r_RNO: 1 loads, 1 LSLICEs Net cap1298_i2c_u1/clk_200khz_RNI6JLJ: 2 loads, 2 LSLICEs Net cap1298_i2c_u1/un31_0_m2_RNIL0721: 4 loads, 4 LSLICEs Net cap1298_i2c_u1/state_RNIAE9M[2]: 1 loads, 1 LSLICEs Net cap1298_i2c_u1/cnt_work_RNI8J9U[0]: 4 loads, 4 LSLICEs Net un1_key_num_1_sqmuxa_i: 6 loads, 6 LSLICEs Net un1_cnt30_i_0: 2 loads, 2 LSLICEs Number of local set/reset loads for net rst_n_in_c merged into GSR: 250 Number of LSRs: 0 Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net cap1298_i2c_u1/state[0]: 43 loads Net cap1298_i2c_u2/state[0]: 43 loads Net cap1298_i2c_u3/state[0]: 42 loads Net cap1298_i2c_u1/clk_200khz_RNI21EE: 25 loads Net cap1298_i2c_u2/clk_200khz_RNI4VGJ: 24 loads Net cap1298_i2c_u3/clk_200khz_RNI6TJO: 24 loads Net cap1298_i2c_u1/state[3]: 19 loads Net cap1298_i2c_u3/state[3]: 19 loads Net cap1298_i2c_u2/state[3]: 18 loads Net cap1298_i2c_u3/state[2]: 16 loads Number of warnings: 1 Number of errors: 0 Design Errors/Warnings WARNING - map: Using local reset signal 'rst_n_in_c' to infer global GSR net. IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ | sda_out[0] | BIDIR | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | scl_out[0] | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ | clk_in | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_2[8] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_2[7] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_2[6] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_2[5] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_2[4] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_2[3] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_2[2] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_2[1] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_2[0] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_1[8] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_1[7] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_1[6] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_1[5] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_1[4] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_1[3] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_1[2] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_1[1] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | segment_led_1[0] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | led_out[7] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | led_out[6] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | led_out[5] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | led_out[4] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | led_out[3] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | led_out[2] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | led_out[1] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | led_out[0] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | sda_out[2] | BIDIR | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | sda_out[1] | BIDIR | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | scl_out[2] | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ | scl_out[1] | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ | rst_n_in | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ Removed logic Block VCC undriven or does not drive anything - clipped. Block display_u/GND undriven or does not drive anything - clipped. Block cap1298_i2c_u1/VCC undriven or does not drive anything - clipped. Block cap1298_i2c_u1/GND undriven or does not drive anything - clipped. Block cap1298_i2c_u2/VCC undriven or does not drive anything - clipped. Block cap1298_i2c_u2/GND undriven or does not drive anything - clipped. Block cap1298_i2c_u3/VCC undriven or does not drive anything - clipped. Block cap1298_i2c_u3/GND undriven or does not drive anything - clipped. Signal rst_n_in_c_i was merged into signal rst_n_in_c Signal sda_out_r_cl_i was merged into signal cap1298_i2c_u1/sda_out_r_cl Signal sda_out_r_cl_0_i was merged into signal cap1298_i2c_u2/sda_out_r_cl_0 Signal sda_out_r_cl_1_i was merged into signal cap1298_i2c_u3/sda_out_r_cl_1 Signal VCC undriven or does not drive anything - clipped. Block rst_n_in_pad_RNIGMQ9 was optimized away. Block cap1298_i2c_u1/sda_out_r_cl_RNI6OQ3 was optimized away. Block cap1298_i2c_u2/sda_out_r_cl_RNI7594 was optimized away. Block cap1298_i2c_u3/sda_out_r_cl_RNI8IN4 was optimized away. Memory Usage GSR Usage --------- GSR Component: The local reset signal 'rst_n_in_c' of the design has been inferred as Global Set Reset (GSR). The reset signal used for GSR control is 'rst_n_in_c'. GSR Property: The design components with GSR property set to ENABLED will respond to global set reset while the components with GSR property set to DISABLED will not. Run Time and Memory Usage ------------------------- Total CPU Time: 1 secs Total REAL Time: 0 secs Peak Memory Usage: 52 MB Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.