Project Settings |
---|
Project Name | proj_1 | Implementation Name | impl1 |
Top Module | JLX12832G_lcd | Pipelining | 1 |
Retiming | 0 | Resource Sharing | 1 |
Fanout Guide | 1000 | Disable I/O Insertion | 0 |
Disable Sequential Optimizations | 0 | Clock Conversion | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
17 |
35 |
0 |
- |
0m:01s |
- |
2017/9/23 19:52:00 |
(premap) | Complete |
3 |
3 |
0 |
0m:01s |
0m:00s |
141MB |
2017/9/23 19:52:02 |
(fpga_mapper) | Complete |
14 |
1 |
0 |
0m:04s |
0m:04s |
178MB |
2017/9/23 19:52:07 |
Multi-srs Generator |
Complete | | | | | | | 2017/9/23 19:52:01 |
Area Summary |
|
Register bits | 119 |
I/O cells | 7 |
Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
ORCA LUTs
(total_luts) | 222 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
JLX12832G_lcd|clk_in | 1.0 MHz | 108.8 MHz | 990.813 |
Optimizations Summary |
Combined Clock Conversion | 1 / 0 |
| |
|