Synthesis Report
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul  4 2016
#install: C:\lscc\diamond\3.8_x64\synpbase
#OS: Windows 7 6.1
#Hostname: TEST-PC

# Wed Nov 01 16:43:31 2017

#Implementation: impl1

Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Synopsys Verilog Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\define_reg.v" (library work)
@I::"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\display.v" (library work)
@I::"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v" (library work)
@I::"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_top.v" (library work)
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module cap1298_top
@N: CG364 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":20:7:20:17|Synthesizing module cap1298_i2c in library work.

@N: CG179 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":243:60:243:64|Removing redundant assignment.
@W: CL169 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Pruning unused register init_num[2:0]. Make sure that there are no unused intermediate registers.
@A: CL282 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Feedback mux created for signal data_wr[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Register bit data_wr[2] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Register bit data_wr[3] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Register bit data_wr[5] is always 0.
@N: CL189 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Register bit data_wr[7] is always 0.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit state_back[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit state_back[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Pruning register bit 7 of data_wr[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Pruning register bit 5 of data_wr[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Pruning register bits 3 to 2 of data_wr[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Pruning register bits 3 to 2 of state_back[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N: CG364 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\display.v":18:7:18:13|Synthesizing module display in library work.

@W: CG294 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\display.v":28:0:28:5|always block should contain at least one event control
@N: CG364 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_top.v":18:7:18:17|Synthesizing module cap1298_top in library work.

@W: CG133 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_top.v":34:12:34:21|Object touch_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_top.v":127:0:127:5|Pruning unused register operate_status_r[8:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_top.v":127:0:127:5|Pruning unused register operate_status[8:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_top.v":65:0:65:5|Pruning unused register key_operate[8:0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_top.v":144:0:144:5|Optimizing register bit cnt[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_top.v":144:0:144:5|Pruning register bit 3 of cnt[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N: CL159 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\display.v":20:8:20:15|Input rst_n_in is unused.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_idle[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_idle[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_idle[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_idle[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_idle[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_read[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_read[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_read[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_work[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_init[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_init[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_init[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Optimizing register bit cnt_init[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Pruning register bits 7 to 4 of cnt_init[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Pruning register bit 4 of cnt_work[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Pruning register bits 4 to 2 of cnt_read[4:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Pruning register bits 7 to 3 of cnt_idle[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N: CL201 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 10 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
@W: CL249 :"C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Initial value is not supported on state machine state

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 76MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Nov 01 16:43:32 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
@N|Running in 64-bit mode
File C:\Users\TEST\Desktop\calculator_cap1298\impl1\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Nov 01 16:43:33 2017

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Nov 01 16:43:33 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
@N|Running in 64-bit mode
File C:\Users\TEST\Desktop\calculator_cap1298\impl1\synwork\cap1298_impl1_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Nov 01 16:43:34 2017

###########################################################]
Pre-mapping Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A: MF827 |No constraint file specified.
@L: C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\impl1\cap1298_impl1_scck.rpt 
Printing clock  summary report in "C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\impl1\cap1298_impl1_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)

@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: BN132 :"c:\users\test\desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Removing sequential instance cap1298_i2c_u3.data_wr[6] because it is equivalent to instance cap1298_i2c_u3.data_wr[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=10  set on top level netlist cap1298_top

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)



Clock Summary
*****************

Start                                      Requested     Requested     Clock                                 Clock                   Clock
Clock                                      Frequency     Period        Type                                  Group                   Load 
------------------------------------------------------------------------------------------------------------------------------------------
cap1298_i2c_0|clk_200khz_derived_clock     1.0 MHz       1000.000      derived (from cap1298_top|clk_in)     Inferred_clkgroup_0     66   
cap1298_i2c_1|clk_200khz_derived_clock     1.0 MHz       1000.000      derived (from cap1298_top|clk_in)     Inferred_clkgroup_0     66   
cap1298_i2c_2|clk_200khz_derived_clock     1.0 MHz       1000.000      derived (from cap1298_top|clk_in)     Inferred_clkgroup_0     66   
cap1298_top|clk_in                         1.0 MHz       1000.000      inferred                              Inferred_clkgroup_0     61   
==========================================================================================================================================

@W: MT529 :"c:\users\test\desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":51:1:51:6|Found inferred clock cap1298_top|clk_in which controls 61 sequential elements including cap1298_i2c_u1.cnt_200khz[5:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

Encoding state machine state[9:0] (in view: work.cap1298_i2c_2(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
Encoding state machine state[9:0] (in view: work.cap1298_i2c_1(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
Encoding state machine state[9:0] (in view: work.cap1298_i2c_0(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 57MB peak: 142MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Nov 01 16:43:37 2017

###########################################################]
Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Available hyper_sources - for debug and ip models
	None Found

@N: FX493 |Applying initial value "00000000" on instance cap1298_i2c_u3.keys_status[7:0] 
@N: FX493 |Applying initial value "00" on instance cap1298_i2c_u3.state_back[1:0] 
@N: FX493 |Applying initial value "00000000" on instance cap1298_i2c_u3.keys_status[7:0] 
@N: FX493 |Applying initial value "00" on instance cap1298_i2c_u3.state_back[1:0] 
@N: FX493 |Applying initial value "00000000" on instance cap1298_i2c_u3.keys_status[7:0] 
@N: FX493 |Applying initial value "00" on instance cap1298_i2c_u3.state_back[1:0] 
@N: FX493 |Applying initial value "00000000000" on instance num_status[10:0] 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)

Encoding state machine state[9:0] (in view: work.cap1298_i2c_2(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
@N:"c:\users\test\desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Found counter in view:work.cap1298_i2c_2(verilog) inst cnt_init[3:0]
@N:"c:\users\test\desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Found counter in view:work.cap1298_i2c_2(verilog) inst cnt_work[3:0]
Encoding state machine state[9:0] (in view: work.cap1298_i2c_1(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
@N:"c:\users\test\desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Found counter in view:work.cap1298_i2c_1(verilog) inst cnt_init[3:0]
@N:"c:\users\test\desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Found counter in view:work.cap1298_i2c_1(verilog) inst cnt_work[3:0]
Encoding state machine state[9:0] (in view: work.cap1298_i2c_0(verilog))
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   0101 -> 0000100000
   0110 -> 0001000000
   0111 -> 0010000000
   1000 -> 0100000000
   1001 -> 1000000000
@N:"c:\users\test\desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Found counter in view:work.cap1298_i2c_0(verilog) inst cnt_init[3:0]
@N:"c:\users\test\desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Found counter in view:work.cap1298_i2c_0(verilog) inst cnt_work[3:0]

Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 147MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 151MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 151MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 152MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 152MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 152MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 152MB)


Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 147MB peak: 152MB)


Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 180MB peak: 182MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:04s		   991.26ns		 632 /       259

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 180MB peak: 182MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 180MB peak: 182MB)

@N: MT611 :|Automatically generated clock cap1298_i2c_0|clk_200khz_derived_clock is not used and is being removed
@N: MT611 :|Automatically generated clock cap1298_i2c_1|clk_200khz_derived_clock is not used and is being removed
@N: MT611 :|Automatically generated clock cap1298_i2c_2|clk_200khz_derived_clock is not used and is being removed


@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 259 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
198 instances converted, 0 sequential instances remain driven by gated/generated clocks

================================ Non-Gated/Non-Generated Clocks =================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance          
-------------------------------------------------------------------------------------------------
@K:CKID0001       clk_in              port                   259        cap1298_i2c_u3.data_wr[4]
=================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 144MB peak: 182MB)

Writing Analyst data base C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\impl1\synwork\cap1298_impl1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 178MB peak: 182MB)

Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\impl1\cap1298_impl1.edi
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 182MB peak: 184MB)


Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 181MB peak: 184MB)

@W: MT420 |Found inferred clock cap1298_top|clk_in with period 1000.00ns. Please declare a user-defined clock on object "p:clk_in"


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Nov 01 16:43:43 2017
#


Top view:               cap1298_top
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary
*******************


Worst slack in design: 990.463

                       Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock         Frequency     Frequency     Period        Period        Slack       Type         Group              
---------------------------------------------------------------------------------------------------------------------------
cap1298_top|clk_in     1.0 MHz       104.9 MHz     1000.000      9.537         990.463     inferred     Inferred_clkgroup_0
===========================================================================================================================





Clock Relationships
*******************

Clocks                                  |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------------------
Starting            Ending              |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------------------
cap1298_top|clk_in  cap1298_top|clk_in  |  1000.000    990.463  |  No paths    -      |  No paths    -      |  No paths    -    
================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: cap1298_top|clk_in
====================================



Starting Points with Worst Slack
********************************

                                  Starting                                                       Arrival            
Instance                          Reference              Type        Pin     Net                 Time        Slack  
                                  Clock                                                                             
--------------------------------------------------------------------------------------------------------------------
cap1298_i2c_u1.keys_status[2]     cap1298_top|clk_in     FD1P3DX     Q       sensor_data1[2]     1.108       990.463
cap1298_i2c_u1.keys_status[4]     cap1298_top|clk_in     FD1P3DX     Q       sensor_data1[4]     1.108       990.463
cap1298_i2c_u1.keys_status[1]     cap1298_top|clk_in     FD1P3DX     Q       sensor_data1[1]     1.148       991.511
cap1298_i2c_u1.keys_status[3]     cap1298_top|clk_in     FD1P3DX     Q       sensor_data1[3]     1.148       991.511
cap1298_i2c_u1.keys_status[6]     cap1298_top|clk_in     FD1P3DX     Q       sensor_data1[6]     1.148       991.511
cap1298_i2c_u2.cnt_write[0]       cap1298_top|clk_in     FD1P3DX     Q       cnt_write[0]        1.188       991.695
cap1298_i2c_u1.cnt_write[0]       cap1298_top|clk_in     FD1P3DX     Q       cnt_write[0]        1.188       991.695
cap1298_i2c_u1.cnt_write[1]       cap1298_top|clk_in     FD1P3DX     Q       cnt_write[1]        1.180       991.703
cap1298_i2c_u2.cnt_write[1]       cap1298_top|clk_in     FD1P3DX     Q       cnt_write[1]        1.180       991.703
cap1298_i2c_u1.read_num[0]        cap1298_top|clk_in     FD1P3BX     Q       read_num[0]         1.236       991.775
====================================================================================================================


Ending Points with Worst Slack
******************************

               Starting                                                     Required            
Instance       Reference              Type        Pin     Net               Time         Slack  
               Clock                                                                            
------------------------------------------------------------------------------------------------
key_num[0]     cap1298_top|clk_in     FD1P3DX     D       key_num_16[0]     1000.089     990.463
key_num[1]     cap1298_top|clk_in     FD1P3DX     D       key_num_16[1]     1000.089     990.463
key_num[4]     cap1298_top|clk_in     FD1P3DX     D       key_num_16[4]     1000.089     990.463
key_num[7]     cap1298_top|clk_in     FD1P3DX     D       key_num_16[7]     1000.089     990.463
key_num[2]     cap1298_top|clk_in     FD1P3DX     D       N_29_i            1000.089     991.479
key_num[3]     cap1298_top|clk_in     FD1P3DX     D       N_31_i            1000.089     991.479
key_num[5]     cap1298_top|clk_in     FD1P3DX     D       N_33_i            1000.089     991.479
key_num[6]     cap1298_top|clk_in     FD1P3DX     D       N_702_i           1000.089     991.479
key_num[8]     cap1298_top|clk_in     FD1P3DX     D       N_704_i           1000.089     991.479
key_num[9]     cap1298_top|clk_in     FD1P3DX     D       N_703_i           1000.089     991.479
================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.089

    - Propagation time:                      9.626
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     990.463

    Number of logic level(s):                8
    Starting point:                          cap1298_i2c_u1.keys_status[2] / Q
    Ending point:                            key_num[0] / D
    The start point is clocked by            cap1298_top|clk_in [rising] on pin CK
    The end   point is clocked by            cap1298_top|clk_in [rising] on pin CK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                              Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
cap1298_i2c_u1.keys_status[2]     FD1P3DX      Q        Out     1.108     1.108       -         
sensor_data1[2]                   Net          -        -       -         -           3         
un1_key_num_1_sqmuxa_0_a3_4       ORCALUT4     A        In      0.000     1.108       -         
un1_key_num_1_sqmuxa_0_a3_4       ORCALUT4     Z        Out     1.089     2.197       -         
N_111                             Net          -        -       -         -           2         
un1_key_num_1_sqmuxa_0_a3_6       ORCALUT4     B        In      0.000     2.197       -         
un1_key_num_1_sqmuxa_0_a3_6       ORCALUT4     Z        Out     1.193     3.389       -         
N_113                             Net          -        -       -         -           4         
key_num_16_0_iv_0_a3_9[0]         ORCALUT4     A        In      0.000     3.389       -         
key_num_16_0_iv_0_a3_9[0]         ORCALUT4     Z        Out     1.153     4.542       -         
N_118                             Net          -        -       -         -           3         
key_num_16_0_iv_0_a3_14[0]        ORCALUT4     B        In      0.000     4.542       -         
key_num_16_0_iv_0_a3_14[0]        ORCALUT4     Z        Out     1.153     5.695       -         
N_141                             Net          -        -       -         -           3         
key_num_16_0_iv_0_a3_3[0]         ORCALUT4     B        In      0.000     5.695       -         
key_num_16_0_iv_0_a3_3[0]         ORCALUT4     Z        Out     1.017     6.712       -         
N_746                             Net          -        -       -         -           1         
key_num_16_0_iv_0_o3[0]           ORCALUT4     C        In      0.000     6.712       -         
key_num_16_0_iv_0_o3[0]           ORCALUT4     Z        Out     1.281     7.993       -         
key_num_16_0_iv_0_o3[0]           Net          -        -       -         -           11        
key_num_16_0_iv_0_a3[0]           ORCALUT4     A        In      0.000     7.993       -         
key_num_16_0_iv_0_a3[0]           ORCALUT4     Z        Out     1.017     9.009       -         
N_721                             Net          -        -       -         -           1         
key_num_16_0_iv_0[0]              ORCALUT4     B        In      0.000     9.009       -         
key_num_16_0_iv_0[0]              ORCALUT4     Z        Out     0.617     9.626       -         
key_num_16[0]                     Net          -        -       -         -           1         
key_num[0]                        FD1P3DX      D        In      0.000     9.626       -         
================================================================================================



##### END OF TIMING REPORT #####]

Constraints that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 182MB peak: 184MB)


Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 182MB peak: 184MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2_4000hc-4

Register bits: 259 of 4320 (6%)
PIC Latch:       0
I/O cells:       34


Details:
BB:             3
FD1P3AX:        9
FD1P3BX:        27
FD1P3DX:        177
FD1S3DX:        43
GSR:            1
IB:             2
INV:            7
OB:             29
OFS1P3BX:       3
ORCALUT4:       619
PFUMX:          3
PUR:            1
VHI:            4
VLO:            5
true:           1
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 32MB peak: 184MB)

Process took 0h:00m:06s realtime, 0h:00m:06s cputime
# Wed Nov 01 16:43:43 2017

###########################################################]