Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.8.0.115.3

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
Tue Sep 19 16:15:35 2017


Command Line:  synthesis -f cap1298_impl1_lattice.synproj -gui 

Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is CSBGA132.
The -d option is LCMXO2-4000HC.
Using package CSBGA132.
Using performance grade 4.
                                                          

##########################################################

### Lattice Family : MachXO2

### Device  : LCMXO2-4000HC

### Package : CSBGA132

### Speed   : 4

##########################################################

                                                          

Optimization goal = Balanced
Top-level module name = pianoshield_top.
Target frequency = 1.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Users/TEST/Desktop/calculator_cap1298 (searchpath added)
-p C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data (searchpath added)
-p C:/Users/TEST/Desktop/calculator_cap1298/impl1 (searchpath added)
-p C:/Users/TEST/Desktop/calculator_cap1298 (searchpath added)
Verilog design file = C:/Users/TEST/Desktop/calculator_cap1298/source/define_reg.v
Verilog design file = C:/Users/TEST/Desktop/calculator_cap1298/source/display.v
Verilog design file = C:/Users/TEST/Desktop/calculator_cap1298/source/pianoshield_top.v
Verilog design file = C:/Users/TEST/Desktop/calculator_cap1298/source/cap1298_i2c.v
NGD file = cap1298_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/users/test/desktop/calculator_cap1298/source/define_reg.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/calculator_cap1298/source/display.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/calculator_cap1298/source/pianoshield_top.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/calculator_cap1298/source/cap1298_i2c.v. VERI-1482
INFO - synthesis: c:/users/test/desktop/calculator_cap1298/source/cap1298_i2c.v(18): analyzing included file c:/users/test/desktop/calculator_cap1298/source/define_reg.v. VERI-1328
Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): pianoshield_top
INFO - synthesis: c:/users/test/desktop/calculator_cap1298/source/pianoshield_top.v(18): compiling module pianoshield_top. VERI-1018
INFO - synthesis: c:/users/test/desktop/calculator_cap1298/source/cap1298_i2c.v(20): compiling module cap1298_i2c. VERI-1018
INFO - synthesis: c:/users/test/desktop/calculator_cap1298/source/display.v(18): compiling module display. VERI-1018
WARNING - synthesis: c:/users/test/desktop/calculator_cap1298/source/display.v(27): net seg does not have a driver. VDB-1002
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
Package Status:                     Final          Version 1.44.
Top-level module name = pianoshield_top.
WARNING - synthesis: c:/users/test/desktop/calculator_cap1298/source/display.v(27): ram seg_original_ramnet has no write-port on it. VDB-1038



WARNING - synthesis: c:/users/test/desktop/calculator_cap1298/source/cap1298_i2c.v(275): Register \cap1298_i2c_u/state_back_i0_i2 is stuck at Zero. VDB-5013
GSR instance connected to net rst_n_in_c.
Applying 1.000000 MHz constraint to all clocks

WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in pianoshield_top_drc.log.
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file cap1298_impl1.ngd.

################### Begin Area Report (pianoshield_top)######################
Number of register bits => 73 of 4635 (1 % )
BB => 1
CCU2D => 9
FD1P3AX => 45
FD1P3AY => 3
FD1P3IX => 12
FD1P3JX => 5
FD1S3AX => 1
FD1S3AY => 1
FD1S3IX => 6
GSR => 1
IB => 2
L6MUX21 => 1
LUT4 => 246
OB => 27
PFUMX => 19
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 2
  Net : clk_in_c, loads : 70
  Net : cap1298_i2c_u/clk_200khz, loads : 14
Clock Enable Nets
Number of Clock Enables: 33
Top 10 highest fanout Clock Enables:
  Net : cap1298_i2c_u/clk_in_c_enable_63, loads : 8
  Net : cap1298_i2c_u/clk_in_c_enable_36, loads : 8
  Net : cap1298_i2c_u/clk_in_c_enable_49, loads : 5
  Net : cap1298_i2c_u/clk_in_c_enable_28, loads : 4
  Net : cap1298_i2c_u/clk_in_c_enable_24, loads : 3
  Net : cap1298_i2c_u/clk_in_c_enable_56, loads : 3
  Net : cap1298_i2c_u/clk_in_c_enable_45, loads : 2
  Net : cap1298_i2c_u/clk_in_c_enable_12, loads : 2
  Net : cap1298_i2c_u/clk_in_c_enable_53, loads : 2
  Net : cap1298_i2c_u/sda_out_N_206, loads : 2
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : cap1298_i2c_u/state_0, loads : 62
  Net : cap1298_i2c_u/state_1, loads : 54
  Net : cap1298_i2c_u/state_2, loads : 52
  Net : cap1298_i2c_u/state_3, loads : 38
  Net : cap1298_i2c_u/cnt_200khz_5__N_84, loads : 17
  Net : cap1298_i2c_u/cnt_work_2, loads : 17
  Net : cap1298_i2c_u/cnt_work_0, loads : 15
  Net : cap1298_i2c_u/cnt_work_3, loads : 15
  Net : rst_n_in_c, loads : 14
  Net : cap1298_i2c_u/cnt_work_1, loads : 13
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk1 [get_nets                          |             |             |
\cap1298_i2c_u/clk_200khz]              |            -|            -|     0  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk0 [get_nets clk_in_c]                |    1.000 MHz|   78.914 MHz|     7  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.


Peak Memory Usage: 63.598  MB

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Elapsed CPU time for LSE flow : 2.714  secs
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