Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version  
Tue Sep 19 16:15:37 2017

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     pianoshield_top
Constraint file:  
Report level:    verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------



================================================================================
Constraint: create_clock -period 1000.000000 -name clk1 [get_nets \cap1298_i2c_u/clk_200khz]
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Constraint: create_clock -period 1000.000000 -name clk0 [get_nets clk_in_c]
            1606 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 987.328ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3IX    CK             \cap1298_i2c_u/cnt_200khz_857__i0  (from clk_in_c +)
   Destination:    FD1P3AX    SP             \cap1298_i2c_u/work_dat_i0_i5  (to clk_in_c +)

   Delay:                  12.387ns  (27.5% logic, 72.5% route), 7 logic levels.

 Constraint Details:

     12.387ns data_path \cap1298_i2c_u/cnt_200khz_857__i0 to \cap1298_i2c_u/work_dat_i0_i5 meets
    1000.000ns delay constraint less
      0.285ns LCE_S requirement (totaling 999.715ns) by 987.328ns

 Path Details: \cap1298_i2c_u/cnt_200khz_857__i0 to \cap1298_i2c_u/work_dat_i0_i5

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              \cap1298_i2c_u/cnt_200khz_857__i0 (from clk_in_c)
Route         2   e 1.198                                  \cap1298_i2c_u/cnt_200khz[0]
LUT4        ---     0.493              A to Z              \cap1298_i2c_u/i931_3_lut
Route         1   e 0.941                                  \cap1298_i2c_u/n6_adj_258
LUT4        ---     0.493              A to Z              \cap1298_i2c_u/i3_4_lut
Route        17   e 1.819                                  \cap1298_i2c_u/cnt_200khz_5__N_84
LUT4        ---     0.493              B to Z              \cap1298_i2c_u/i144_2_lut_rep_99_3_lut
Route         8   e 1.540                                  \cap1298_i2c_u/n5803
LUT4        ---     0.493              B to Z              \cap1298_i2c_u/i1_2_lut_rep_88_3_lut_4_lut
Route         5   e 1.405                                  n5792
LUT4        ---     0.493              A to Z              i3_4_lut
Route         2   e 1.141                                  n5296
LUT4        ---     0.493              B to Z              \cap1298_i2c_u/i5233_2_lut
Route         1   e 0.941                                  \cap1298_i2c_u/clk_in_c_enable_13
                  --------
                   12.387  (27.5% logic, 72.5% route), 7 logic levels.


Passed:  The following path meets requirements by 987.328ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3IX    CK             \cap1298_i2c_u/cnt_200khz_857__i0  (from clk_in_c +)
   Destination:    FD1P3AX    SP             \cap1298_i2c_u/work_dat_i0_i1  (to clk_in_c +)

   Delay:                  12.387ns  (27.5% logic, 72.5% route), 7 logic levels.

 Constraint Details:

     12.387ns data_path \cap1298_i2c_u/cnt_200khz_857__i0 to \cap1298_i2c_u/work_dat_i0_i1 meets
    1000.000ns delay constraint less
      0.285ns LCE_S requirement (totaling 999.715ns) by 987.328ns

 Path Details: \cap1298_i2c_u/cnt_200khz_857__i0 to \cap1298_i2c_u/work_dat_i0_i1

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              \cap1298_i2c_u/cnt_200khz_857__i0 (from clk_in_c)
Route         2   e 1.198                                  \cap1298_i2c_u/cnt_200khz[0]
LUT4        ---     0.493              A to Z              \cap1298_i2c_u/i931_3_lut
Route         1   e 0.941                                  \cap1298_i2c_u/n6_adj_258
LUT4        ---     0.493              A to Z              \cap1298_i2c_u/i3_4_lut
Route        17   e 1.819                                  \cap1298_i2c_u/cnt_200khz_5__N_84
LUT4        ---     0.493              B to Z              \cap1298_i2c_u/i144_2_lut_rep_99_3_lut
Route         8   e 1.540                                  \cap1298_i2c_u/n5803
LUT4        ---     0.493              B to Z              \cap1298_i2c_u/i1_2_lut_rep_88_3_lut_4_lut
Route         5   e 1.405                                  n5792
LUT4        ---     0.493              A to Z              i3_4_lut
Route         2   e 1.141                                  n5296
LUT4        ---     0.493              B to Z              \cap1298_i2c_u/i5226_2_lut
Route         1   e 0.941                                  \cap1298_i2c_u/clk_in_c_enable_15
                  --------
                   12.387  (27.5% logic, 72.5% route), 7 logic levels.


Passed:  The following path meets requirements by 987.328ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3IX    CK             \cap1298_i2c_u/cnt_200khz_857__i1  (from clk_in_c +)
   Destination:    FD1P3AX    SP             \cap1298_i2c_u/work_dat_i0_i5  (to clk_in_c +)

   Delay:                  12.387ns  (27.5% logic, 72.5% route), 7 logic levels.

 Constraint Details:

     12.387ns data_path \cap1298_i2c_u/cnt_200khz_857__i1 to \cap1298_i2c_u/work_dat_i0_i5 meets
    1000.000ns delay constraint less
      0.285ns LCE_S requirement (totaling 999.715ns) by 987.328ns

 Path Details: \cap1298_i2c_u/cnt_200khz_857__i1 to \cap1298_i2c_u/work_dat_i0_i5

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              \cap1298_i2c_u/cnt_200khz_857__i1 (from clk_in_c)
Route         2   e 1.198                                  \cap1298_i2c_u/cnt_200khz[1]
LUT4        ---     0.493              C to Z              \cap1298_i2c_u/i931_3_lut
Route         1   e 0.941                                  \cap1298_i2c_u/n6_adj_258
LUT4        ---     0.493              A to Z              \cap1298_i2c_u/i3_4_lut
Route        17   e 1.819                                  \cap1298_i2c_u/cnt_200khz_5__N_84
LUT4        ---     0.493              B to Z              \cap1298_i2c_u/i144_2_lut_rep_99_3_lut
Route         8   e 1.540                                  \cap1298_i2c_u/n5803
LUT4        ---     0.493              B to Z              \cap1298_i2c_u/i1_2_lut_rep_88_3_lut_4_lut
Route         5   e 1.405                                  n5792
LUT4        ---     0.493              A to Z              i3_4_lut
Route         2   e 1.141                                  n5296
LUT4        ---     0.493              B to Z              \cap1298_i2c_u/i5233_2_lut
Route         1   e 0.941                                  \cap1298_i2c_u/clk_in_c_enable_13
                  --------
                   12.387  (27.5% logic, 72.5% route), 7 logic levels.

Report: 12.672 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk1 [get_nets                          |             |             |
\cap1298_i2c_u/clk_200khz]              |            -|            -|     0  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk0 [get_nets clk_in_c]                |  1000.000 ns|    12.672 ns|     7  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.



Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover  1689 paths, 268 nets, and 853 connections (74.0% coverage)


Peak memory: 66129920 bytes, TRCE: 2744320 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs