Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.8.0.115.3

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
Wed Nov 01 17:02:33 2017


Command Line:  synthesis -f calculator_lcd_impl1_lattice.synproj -gui -msgset C:/Users/TEST/Desktop/calculator_fpga/calculator_lcd/promote.xml 

Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is CSBGA132.
The -d option is LCMXO2-4000HC.
Using package CSBGA132.
Using performance grade 4.
                                                          

##########################################################

### Lattice Family : MachXO2

### Device  : LCMXO2-4000HC

### Package : CSBGA132

### Speed   : 4

##########################################################

                                                          

Optimization goal = Balanced
Top-level module name = calculator_lcd.
Target frequency = 1.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Users/TEST/Desktop/calculator_fpga/calculator_lcd (searchpath added)
-p C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data (searchpath added)
-p C:/Users/TEST/Desktop/calculator_fpga/calculator_lcd/impl1 (searchpath added)
-p C:/Users/TEST/Desktop/calculator_fpga/calculator_lcd (searchpath added)
Verilog design file = C:/Users/TEST/Desktop/calculator_fpga/calculator_lcd/calculator_lcd.v
NGD file = calculator_lcd_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): calculator_lcd
INFO - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(9): compiling module calculator_lcd. VERI-1018
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(62): index 13 is out of range [12:0] for cmd_r. VERI-1216
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(63): index 14 is out of range [12:0] for cmd_r. VERI-1216
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(64): index 15 is out of range [12:0] for cmd_r. VERI-1216
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(65): index 16 is out of range [12:0] for cmd_r. VERI-1216
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(66): index 17 is out of range [12:0] for cmd_r. VERI-1216
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(67): index 18 is out of range [12:0] for cmd_r. VERI-1216
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(116): expression size 32 truncated to fit in target size 16. VERI-1209
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(169): expression size 32 truncated to fit in target size 8. VERI-1209
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(249): expression size 32 truncated to fit in target size 4. VERI-1209
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(263): expression size 32 truncated to fit in target size 9. VERI-1209
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(288): expression size 32 truncated to fit in target size 9. VERI-1209
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(305): expression size 32 truncated to fit in target size 26. VERI-1209
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(70): net mem does not have a driver. VDB-1002
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
Package Status:                     Final          Version 1.44.
Top-level module name = calculator_lcd.
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(70): ram mem_original_ramnet has no write-port on it. VDB-1038



WARNING - synthesis: Bit 14 of Register temp is stuck at Zero
WARNING - synthesis: Bit 26 of Register temp is stuck at Zero
WARNING - synthesis: Bit 54 of Register temp is stuck at Zero
WARNING - synthesis: Bit 0 of Register char_reg__0 is stuck at Zero
WARNING - synthesis: Bit 1 of Register char_reg__0 is stuck at Zero
WARNING - synthesis: Bit 2 of Register char_reg__0 is stuck at Zero
WARNING - synthesis: Bit 3 of Register char_reg__0 is stuck at Zero
WARNING - synthesis: Bit 0 of Register temp is stuck at Zero
WARNING - synthesis: Bit 1 of Register temp is stuck at Zero
WARNING - synthesis: Bit 2 of Register temp is stuck at Zero
WARNING - synthesis: Bit 3 of Register temp is stuck at Zero
WARNING - synthesis: Bit 4 of Register temp is stuck at Zero
WARNING - synthesis: Bit 5 of Register temp is stuck at Zero
WARNING - synthesis: Bit 6 of Register temp is stuck at Zero
WARNING - synthesis: Bit 7 of Register temp is stuck at Zero
WARNING - synthesis: Bit 8 of Register temp is stuck at Zero
WARNING - synthesis: Bit 10 of Register temp is stuck at Zero
WARNING - synthesis: Bit 11 of Register temp is stuck at Zero
WARNING - synthesis: Bit 12 of Register temp is stuck at Zero
WARNING - synthesis: Bit 13 of Register temp is stuck at Zero
WARNING - synthesis: Bit 14 of Register temp is stuck at Zero
WARNING - synthesis: Bit 15 of Register temp is stuck at Zero
WARNING - synthesis: Bit 18 of Register temp is stuck at Zero
WARNING - synthesis: Bit 19 of Register temp is stuck at Zero
WARNING - synthesis: Bit 20 of Register temp is stuck at Zero
WARNING - synthesis: Bit 21 of Register temp is stuck at Zero
WARNING - synthesis: Bit 22 of Register temp is stuck at Zero
WARNING - synthesis: Bit 23 of Register temp is stuck at Zero
WARNING - synthesis: Bit 25 of Register temp is stuck at Zero
WARNING - synthesis: Bit 26 of Register temp is stuck at Zero
WARNING - synthesis: Bit 27 of Register temp is stuck at Zero
WARNING - synthesis: Bit 28 of Register temp is stuck at Zero
WARNING - synthesis: Bit 32 of Register temp is stuck at One
WARNING - synthesis: Bit 33 of Register temp is stuck at One
WARNING - synthesis: Bit 37 of Register temp is stuck at Zero
WARNING - synthesis: Bit 38 of Register temp is stuck at Zero
WARNING - synthesis: Bit 39 of Register temp is stuck at Zero
WARNING - synthesis: Bit 40 of Register temp is stuck at Zero
WARNING - synthesis: Bit 41 of Register temp is stuck at Zero
WARNING - synthesis: Bit 42 of Register temp is stuck at Zero
WARNING - synthesis: Bit 43 of Register temp is stuck at Zero
WARNING - synthesis: Bit 44 of Register temp is stuck at Zero
WARNING - synthesis: Bit 45 of Register temp is stuck at Zero
WARNING - synthesis: Bit 46 of Register temp is stuck at Zero
WARNING - synthesis: Bit 47 of Register temp is stuck at Zero
WARNING - synthesis: Bit 48 of Register temp is stuck at Zero
WARNING - synthesis: Bit 49 of Register temp is stuck at Zero
WARNING - synthesis: Bit 50 of Register temp is stuck at Zero
WARNING - synthesis: Bit 51 of Register temp is stuck at Zero
WARNING - synthesis: Bit 52 of Register temp is stuck at Zero
WARNING - synthesis: Bit 53 of Register temp is stuck at Zero
WARNING - synthesis: Bit 54 of Register temp is stuck at Zero
WARNING - synthesis: Bit 55 of Register temp is stuck at Zero
WARNING - synthesis: Bit 56 of Register temp is stuck at Zero
WARNING - synthesis: Bit 57 of Register temp is stuck at Zero
WARNING - synthesis: Bit 58 of Register temp is stuck at Zero
WARNING - synthesis: Bit 0 of Register data_state_back is stuck at Zero
WARNING - synthesis: Bit 1 of Register data_state_back is stuck at Zero
WARNING - synthesis: Bit 2 of Register data_state_back is stuck at Zero
WARNING - synthesis: Bit 3 of Register data_state_back is stuck at Zero
WARNING - synthesis: Bit 4 of Register data_state_back is stuck at Zero
WARNING - synthesis: Bit 7 of Register data_state_back is stuck at Zero
WARNING - synthesis: c:/users/test/desktop/calculator_fpga/calculator_lcd/calculator_lcd.v(309): Register data_state_i0_i7 is stuck at Zero. VDB-5013
GSR instance connected to net rst_n_c.
Duplicate register/latch removal. temp__i3 is a one-to-one match with temp__i2.
Applying 1.000000 MHz constraint to all clocks

WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in calculator_lcd_drc.log.
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file calculator_lcd_impl1.ngd.

################### Begin Area Report (calculator_lcd)######################
Number of register bits => 83 of 4635 (1 % )
CCU2D => 27
FD1P3AX => 33
FD1P3AY => 1
FD1P3IX => 30
FD1S3AX => 2
FD1S3IX => 17
GSR => 1
IB => 2
LUT4 => 187
OB => 5
PFUMX => 9
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 1
  Net : clk_c, loads : 83
Clock Enable Nets
Number of Clock Enables: 15
Top 10 highest fanout Clock Enables:
  Net : clk_c_enable_58, loads : 14
  Net : rst_n_c, loads : 13
  Net : clk_c_enable_57, loads : 12
  Net : clk_c_enable_55, loads : 10
  Net : clk_c_enable_63, loads : 10
  Net : clk_c_enable_60, loads : 8
  Net : clk_c_enable_15, loads : 4
  Net : clk_c_enable_62, loads : 3
  Net : clk_c_enable_13, loads : 2
  Net : clk_c_enable_26, loads : 2
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : data_state_0, loads : 31
  Net : data_state_1, loads : 28
  Net : data_state_cnt_4, loads : 26
  Net : data_state_cnt_3, loads : 23
  Net : data_state_cnt_2, loads : 21
  Net : data_state_2, loads : 20
  Net : data_state_cnt_0, loads : 20
  Net : data_state_cnt_5, loads : 16
  Net : data_state_cnt_1, loads : 16
  Net : n6016, loads : 16
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk0 [get_nets clk_c]                   |    1.000 MHz|   48.797 MHz|    12  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.


Peak Memory Usage: 73.223  MB

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Elapsed CPU time for LSE flow : 2.855  secs
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