Project Settings
Project Name proj_1 Implementation Name impl1
Top Module calculator Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 1000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 Clock Conversion 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 40 121 0 - 0m:02s - 2017/10/26
14:30:52
(premap)Complete 2 3 0 0m:01s 0m:01s 142MB 2017/10/26
14:30:55
(fpga_mapper)Complete 33 5 0 0m:17s 0m:17s 206MB 2017/10/26
14:31:13
Multi-srs Generator Complete0m:01s2017/10/26
14:30:53

Area Summary
Register bits 254 I/O cells 39
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 781

Timing Summary
Clock NameReq FreqEst FreqSlack
calculator|clk_in1.0 MHz11.3 MHz911.725

Optimizations Summary
Combined Clock Conversion 1 / 0