在 Verilog 中有两种移位运算符：左移位运算符和右移位运算符，这两种移位运算符都用 0来填补移出的空位。如下。

例子:<<操作。
//In this example, the reg result is assigned the binary value 0100,
// which is 0001 shifted to the left two positions and zero-filled.
module shift;
  reg [3:0] start, result;
  initial begin
    start = 1;
    result = (start << 2);
  end
endmodule