在小脚丫FPGA板上做一个综合性的组合逻辑项目，用4个按键和4个开关作为加法器的输入，将加法以后的结果在2个数码管上显示出来。4位按键和4位开关能够支持的最大输入数字位15，加法以后的最大值30，左侧的数码管，代表十进制数的十位显示的数字为0、1、2、3，右侧的数码管代表十进制的个位显示的数字为0-9。

另外为了观察加法器的每一个进位的状态，使用板上的4个LED分别显示4个进位位的信息。

• 组合逻辑中的加法器 - 半加器、全加器
• 组合逻辑中的解码器 - BCD码到数码管的显示
• 组合逻辑中的编码器 - 二进制到BCD解码
• Verilog的语法

module adder_4bits(sw,key,seg_led_1,seg_led_2,led_carry);
input [3:0] sw;
input [3:0] key;
output [8:0] seg_led_1;
output [8:0] seg_led_2;
output [3:0] led_carry;
 
wire [3:0] input1;
wire [3:0] input2;
wire [3:0] answer;
 
wire  carry_out;
wire [3:0] carry;
 
assign input1 = sw;
assign input2 = ~key;
 
genvar i;
generate 
   for(i=0;i<4;i=i+1)
       begin: generate_N_bit_Adder
   if(i==0) 
       half_adder f(input1[0],input2[0],answer[0],carry[0]);
   else
       full_adder f(input1[i],input2[i],carry[i-1],answer[i],carry[i]);
     end
   assign carry_out = carry[3];
endgenerate
 
 
assign led_carry = ~carry;
 
wire [4:0] sum;
assign sum = {carry_out,answer};
 
wire [3:0] seg1_input;
wire [3:0] seg2_input;
 
binary2bcd b2b(sum,seg1_input,seg2_input);
 
LED display_answer(seg1_input,seg2_input,seg_led_1,seg_led_2);
 
endmodule 
 
 
module half_adder(x,y,s,c);
   input x,y;
   output s,c;
   assign s=x^y;
   assign c=x&y;
endmodule // half adder
 
module full_adder(x,y,c_in,s,c_out);
   input x,y,c_in;
   output s,c_out;
 assign s = (x^y) ^ c_in;
 assign c_out = (y&c_in)| (x&y) | (x&c_in);
endmodule // full_adder

module binary2bcd(binarydata,tens,ones); input [4:0] binarydata; output reg [3:0] tens; output reg [3:0] ones;

always @* case(binary_data)

  5'd0: 
      begin
          tens = 4'd0;
          ones = 4'd0;
      end
  5'd1:
      begin
          tens = 4'd0;
          ones = 4'd1;
      end
  5'd2:
      begin
          tens = 4'd0;
          ones = 4'd2;
      end
  5'd3:
      begin
          tens = 4'd0;
          ones = 4'd3;
      end
  5'd4:
      begin
          tens = 4'd0;
          ones = 4'd4;
      end
  5'd5:
      begin
          tens = 4'd0;
          ones = 4'd5;
      end
  5'd6:
      begin
          tens = 4'd0;
          ones = 4'd6;
      end
  5'd7:
      begin
          tens = 4'd0;
          ones = 4'd7;
      end
  5'd8:
      begin
          tens = 4'd0;
          ones = 4'd8;
      end
  5'd9:
      begin
          tens = 4'd0;
          ones = 4'd9;
      end
  5'd10: 
      begin
          tens = 4'd1;
          ones = 4'd0;
      end
  5'd11:
      begin
          tens = 4'd1;
          ones = 4'd1;
      end
  5'd12:
      begin
          tens = 4'd1;
          ones = 4'd2;
      end
  5'd13:
      begin
          tens = 4'd1;
          ones = 4'd3;
      end
  5'd14:
      begin
          tens = 4'd1;
          ones = 4'd4;
      end
  5'd15:
      begin
          tens = 4'd1;
          ones = 4'd5;
      end
  5'd16:
      begin
          tens = 4'd1;
          ones = 4'd6;
      end
  5'd17:
      begin
          tens = 4'd1;
          ones = 4'd7;
      end
  5'd18:
      begin
          tens = 4'd1;
          ones = 4'd8;
      end
  5'd19:
      begin
          tens = 4'd1;
          ones = 4'd9;
      end
  5'd20: 
      begin
          tens = 4'd2;
          ones = 4'd0;
      end
  5'd21:
      begin
          tens = 4'd2;
          ones = 4'd1;
      end
  5'd22:
      begin
          tens = 4'd2;
          ones = 4'd2;
      end
  5'd23:
      begin
          tens = 4'd2;
          ones = 4'd3;
      end
  5'd24:
      begin
          tens = 4'd2;
          ones = 4'd4;
      end
  5'd25:
      begin
          tens = 4'd2;
          ones = 4'd5;
      end
  5'd26:
      begin
          tens = 4'd2;
          ones = 4'd6;
      end
  5'd27:
      begin
          tens = 4'd2;
          ones = 4'd7;
      end
  5'd28:
      begin
          tens = 4'd2;
          ones = 4'd8;
      end
  5'd29:
      begin
          tens = 4'd2;
          ones = 4'd9;
      end
  5'd30:
      begin
          tens = 4'd3;
          ones = 4'd0;
      end
  5'd31:
      begin
          tens = 4'd3;
          ones = 4'd1;
      end

endcase

/* integer i;

always @(binarydata) begin tens = 4'd0; ones = 4'd0;
for (i=7; i >= 0; i=i-1) begin if (tens>=5) tens = tens +3; if (ones >= 5) ones = ones +3; tens = tens « 1; tens[0] = ones[3]; ones = ones « 1; ones[0] = binarydata[i];

  end

end */

endmodule