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| 两侧同时换到之前的修订记录 前一修订版 后一修订版 | 前一修订版 | ||
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blink [2016/06/02 14:02] anran |
blink [2016/08/03 19:28] (当前版本) zhijun |
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| 行 5: | 行 5: | ||
| // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< | ||
| // -------------------------------------------------------------------- | // -------------------------------------------------------------------- | ||
| - | // Module: Blink | + | // File name : blink.v |
| - | // | + | // Module name : blink |
| - | // Author: Step | + | // Author : Step |
| - | // | + | // Description : Flashing LED under a second clock cycle |
| - | // Description: LED Blink | + | // Web : www.stepfpga.com |
| - | // | + | |
| - | // Web: www.ecbcamp.com | + | |
| // | // | ||
| // -------------------------------------------------------------------- | // -------------------------------------------------------------------- | ||
| 行 19: | 行 17: | ||
| // V1.0 |2015/11/11 |Initial ver | // V1.0 |2015/11/11 |Initial ver | ||
| // -------------------------------------------------------------------- | // -------------------------------------------------------------------- | ||
| - | module Blink # | + | module blink |
| ( | ( | ||
| - | parameter CNT_NUM = 12500000 | + | clk_in, |
| - | ) | + | rst_n_in, |
| - | ( | + | led_out |
| - | input clk_in, | + | |
| - | input rst_n_in, | + | |
| - | output led_out | + | |
| ); | ); | ||
| - | reg [23:0] cnt = 24'd0; | + | parameter CNT_NUM = 12500000; |
| - | reg clk_div = 1; | + | |
| - | always@(posedge clk_in or negedge rst_n_in) begin | + | reg [23:0] cnt; |
| - | if(!rst_n_in) begin | + | reg clk_div; |
| + | |||
| + | always @(posedge clk_in or negedge rst_n_in) | ||
| + | begin | ||
| + | if(!rst_n_in) | ||
| + | begin | ||
| cnt <= 24'd0; | cnt <= 24'd0; | ||
| clk_div <= 1; | clk_div <= 1; | ||
| - | end else begin | + | end |
| - | if(cnt>=CNT_NUM-1) begin | + | else |
| + | begin | ||
| + | if(cnt>=CNT_NUM-1) | ||
| + | begin | ||
| cnt <= 24'd0; | cnt <= 24'd0; | ||
| clk_div <= ~clk_div; | clk_div <= ~clk_div; | ||
| - | end else cnt <= cnt + 1; | + | end |
| - | end | + | else |
| + | cnt <= cnt + 1; | ||
| + | end | ||
| end | end | ||