显示页面 讨论 修订记录 反向链接 本页面只读。您可以查看源文件，但不能更改它。如果您觉得这是系统错误，请联系管理员。 A digital clock manager (DCM) is an electronic component available on some FPGAs (notably ones produced by Xilinx). A DCM is useful for manipulating clock signals inside the FPGA, and to avoid clock skew which would introduce errors in the circuit. ====Uses of DCM==== * DCMs have the following applications:[1] * Multipling or dividing an incoming clock (which can come for outside the FPGA or from a Digital Frequency Syntetizer [DFS]). * Making sure the clock has a steady duty cycle. * Adding a phase shift with the additional use of a Delay-locked loop. * Eliminating clock skew within an FPGA design. ====See also==== * Clock signal * Delay-locked loop * Phase-locked loop