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| 后一修订版 | 前一修订版 | ||
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dled_disp [2016/05/30 15:12] anran 创建 |
dled_disp [2016/06/01 13:57] (当前版本) anran |
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| 行 1: | 行 1: | ||
| - | ''// -------------------------------------------------------------------- | + | ====DLED_DISP程序==== |
| + | <code verilog> | ||
| + | // -------------------------------------------------------------------- | ||
| // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< | ||
| // -------------------------------------------------------------------- | // -------------------------------------------------------------------- | ||
| 行 26: | 行 28: | ||
| ); | ); | ||
| - | parameter CLK_DIV_PERIOD=1000; //related with clk_div's frequency | + | parameter CLK_DIV_PERIOD=3900; //related with clk_div's frequency |
| parameter DELAY_PERIOD=10000; //related with delay time and refresh frequency | parameter DELAY_PERIOD=10000; //related with delay time and refresh frequency | ||
| parameter CLK_DIV_PULSE_PERIOD=25000000; //related with clk_div_pulse_out's frequency | parameter CLK_DIV_PULSE_PERIOD=25000000; //related with clk_div_pulse_out's frequency | ||
| 行 53: | 行 55: | ||
| mem[8]= 8'h7f; // 8 | mem[8]= 8'h7f; // 8 | ||
| mem[9]= 8'h6f; // 9 | mem[9]= 8'h6f; // 9 | ||
| - | mem[10]= 8'h77; // A | + | mem[10]= 8'h77; // A |
| mem[11]= 8'h40; // b | mem[11]= 8'h40; // b | ||
| mem[12]= 8'h39; // C | mem[12]= 8'h39; // C | ||
| 行 101: | 行 103: | ||
| //clk_div = clk_in/CLK_DIV_PERIOD | //clk_div = clk_in/CLK_DIV_PERIOD | ||
| reg clk_div; | reg clk_div; | ||
| - | reg[15:0] clk_cnt=0; | + | reg[11:0] clk_cnt=0; |
| always@(posedge clk_in or negedge rst_n_in) begin | always@(posedge clk_in or negedge rst_n_in) begin | ||
| if(!rst_n_in) clk_cnt<=0; | if(!rst_n_in) clk_cnt<=0; | ||
| 行 165: | 行 167: | ||
| data_state<=WRITE;data_state_back<=IDLE; | data_state<=WRITE;data_state_back<=IDLE; | ||
| end | end | ||
| - | 4: begin data_state<=DELAY;data_state_back<=IDLE; end | + | 4: begin data_state_cnt<=0; end |
| - | 5: begin data_state_cnt<=0; end | + | |
| default; | default; | ||
| endcase | endcase | ||
| 行 206: | 行 207: | ||
| endmodule | endmodule | ||
| - | '' | + | |
| + | </code> | ||