差别
这里会显示出您选择的修订版和当前版本之间的差别。
|
fpga的配置 [2017/09/11 02:13] gongyu 创建 |
fpga的配置 [2017/09/11 02:14] (当前版本) gongyu |
||
|---|---|---|---|
| 行 44: | 行 44: | ||
| Here's a description of the five most important pins of this interface: | Here's a description of the five most important pins of this interface: | ||
| - | ^Xilinx pin name ^Altera pin name ^Direction ^Pin function | + | ^Xilinx pin name ^Altera pin name ^Direction ^Pin function^ |
| - | ^data ^data0 ^FPGA input ^configuration data bit | + | ^data ^data0 ^FPGA input ^configuration data bit^ |
| - | ^clk ^dclk ^FPGA input ^configuration clock (the configuration data bit is shifted in the FPGA at the clock rising-edge) | + | ^clk ^dclk ^FPGA input ^configuration clock (the configuration data bit is shifted in the FPGA at the clock rising-edge)^ |
| - | ^prog_b ^nConfig ^FPGA input ^When asserted (i.e. when it goes low - this is an active low pin), the FPGA is reset-ed and looses its configuration. If the FPGA was in user-mode, it stops operation immediately, and all IOs become inactive. | + | ^prog_b ^nConfig ^FPGA input ^When asserted (i.e. when it goes low - this is an active low pin), the FPGA is reset-ed and looses its configuration. If the FPGA was in user-mode, it stops operation immediately, and all IOs become inactive.^ |
| - | ^init_b ^nStatus ^FPGA output ^This pin indicates when the FPGA is ready to start the configuration process (it takes a few milliseconds for the FPGA to get ready). | + | ^init_b ^nStatus ^FPGA output ^This pin indicates when the FPGA is ready to start the configuration process (it takes a few milliseconds for the FPGA to get ready).^ |
| - | ^done ^ConfDone ^FPGA output ^When high, indicates that the FPGA is configured (i.e. in user-mode). | + | ^done ^ConfDone ^FPGA output ^When high, indicates that the FPGA is configured (i.e. in user-mode).^ |
| Note: the init_b and done pins are actually open-collector pins, so pull-up resistors are required on these. Also if multiple FPGAs are to be configured, these pins are usually connected together so that all the FPGAs switch into "user-mode" together. There is many more details, so for a complete description, check your FPGA datasheet. | Note: the init_b and done pins are actually open-collector pins, so pull-up resistors are required on these. Also if multiple FPGAs are to be configured, these pins are usually connected together so that all the FPGAs switch into "user-mode" together. There is many more details, so for a complete description, check your FPGA datasheet. | ||