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nbit_adder [2021/10/03 02:12] gongyu 创建 |
nbit_adder [2021/10/03 02:12] (当前版本) gongyu |
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| ## N位加法器设计 | ## N位加法器设计 | ||
| 来自[[https://www.fpga4student.com/2017/07/n-bit-adder-design-in-verilog.html|来自FPGA4student]] | 来自[[https://www.fpga4student.com/2017/07/n-bit-adder-design-in-verilog.html|来自FPGA4student]] | ||
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| The next Verilog/ VHDL project is a complete co-processor specially designed for cryptographic applications. The co-processor has standard instructions and dedicated function units specific for security. The co-processor is implemented mainly in VHDL, but the N-bit Adder is designed in Verilog. The Verilog code for the N-bit Adder will be instantiated later in a VHDL design. In next posts, implementations of major modules in the co-processor will be presented. The complete co-processor design and implementation will be presented after every part of the co-processor is posted. | The next Verilog/ VHDL project is a complete co-processor specially designed for cryptographic applications. The co-processor has standard instructions and dedicated function units specific for security. The co-processor is implemented mainly in VHDL, but the N-bit Adder is designed in Verilog. The Verilog code for the N-bit Adder will be instantiated later in a VHDL design. In next posts, implementations of major modules in the co-processor will be presented. The complete co-processor design and implementation will be presented after every part of the co-processor is posted. | ||
| This post presents Verilog code for N-bit Adder designed for the co-processor. The Verilog code for N-bit Adder is done by using Structural Modeling. | This post presents Verilog code for N-bit Adder designed for the co-processor. The Verilog code for N-bit Adder is done by using Structural Modeling. | ||